Semiconductor device and method for manufacturing the same

ABSTRACT

A miniaturized transistor, a transistor with low parasitic capacitance, a transistor with high frequency characteristics, or a semiconductor device including the transistor is provided. The semiconductor device includes a first insulator, an oxide semiconductor over the first insulator, a first conductor and a second conductor that are in contact with the oxide semiconductor, a second insulator that is over the first and second conductors and has an opening reaching the oxide semiconductor, a third insulator over the oxide semiconductor and the second insulator, and a fourth conductor over the third insulator. The first conductor includes a first region and a second region. The second conductor includes a third region and a fourth region. The second region faces the third region with the first conductor and the first insulator interposed therebetween. The second region is thinner than the first region. The third region is thinner than the fourth region.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a transistor and a semiconductor device, and a manufacturing method thereof, for example. The present invention relates to a display device, a light-emitting device, a lighting device, a power storage device, a memory device, a processor, or an electronic device, for example. The present invention relates to a method for manufacturing a display device, a liquid crystal display device, a light-emitting device, a memory device, or an electronic device. The present invention relates to a driving method of a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a memory device, or an electronic device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter.

In this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A display device, a light-emitting device, a lighting device, an electro-optical device, a semiconductor circuit, and an electronic device include a semiconductor device in some cases.

2. Description of the Related Art

In recent years, a transistor including an oxide semiconductor has attracted attention. An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for a semiconductor of a transistor in a large display device. In addition, there is an advantage in a transistor including an oxide semiconductor that capital investment can be reduced because part of production equipment for a transistor including amorphous silicon can be retrofitted and utilized.

It is known that a transistor including an oxide semiconductor has an extremely low leakage current in an off state. For example, a low-power CPU and the like utilizing the characteristics that a leakage current of the transistor including an oxide semiconductor is low is disclosed (see Patent Document 1).

A method for manufacturing a transistor including an oxide semiconductor by forming a gate electrode so as to fill an opening is disclosed (see Patent Document 2 and Patent Document 3).

REFERENCE Patent Document

-   [Patent Document 1] Japanese Published Patent Application No.     2012-257187 -   [Patent Document 2] Japanese Published Patent Application No.     2014-241407 -   [Patent Document 3] Japanese Published Patent Application No.     2014-240833

SUMMARY OF THE INVENTION

An object is to provide a minute transistor. Another object is to provide a transistor with low parasitic capacitance. Another object is to provide a transistor with high frequency characteristics. Another object is to provide a transistor with favorable electrical characteristics. Another object is to provide a transistor with stable electrical characteristics. Another object is to provide a transistor with low off-state current. Another object is to provide a novel transistor. Another object is to provide a semiconductor device including the transistor. Another object is to provide a semiconductor device that can operate at high speed. Another object is to provide a novel semiconductor device. Another object is to provide a module including the semiconductor device. Another object is to provide an electronic device including the semiconductor device or the module.

Note that the descriptions of these objects do not disturb the existence of other objects. In one embodiment of the present invention, there is no need to achieve all the objects. Other objects are apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.

(1) One embodiment of the present invention is a semiconductor device including an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor includes a first region, a second region, and a third region. The first region includes a region where the first conductor overlaps with the oxide semiconductor with the first insulator interposed therebetween. The second region includes a region where the first conductor overlaps with the second conductor with the first insulator and the second insulator interposed therebetween. The third region includes a region where the first conductor overlaps with the third conductor with the first insulator and the second insulator interposed therebetween. The oxide semiconductor includes a fourth region and a fifth region. The fourth region includes a region where the oxide semiconductor is in contact with the second conductor. The fifth region includes a region where the oxide semiconductor is in contact with the third conductor. The second conductor includes a sixth region and a seventh region. The third conductor includes an eighth region and a ninth region. The seventh region faces the eighth region with the first conductor and the first insulator interposed therebetween. The seventh region is thinner than the sixth region. The eighth region is thinner than the ninth region. (2) Another embodiment of the present invention is the semiconductor device according to (1) in which the first conductor is a stacked-layer film including a conductor that is less likely to transmit oxygen. (3) Another embodiment of the present invention is the semiconductor device according to (1) or (2) in which the second conductor and the third conductor are each a stacked-layer film including a conductor that is less likely to transmit oxygen. (4) Another embodiment of the present invention is the semiconductor device according to any one of (1) to (3) in which the oxide semiconductor includes a first oxide semiconductor layer and a second oxide semiconductor layer, and the first oxide semiconductor layer overlaps with the second oxide semiconductor layer. (5) Another embodiment of the present invention is the semiconductor device according to any one of (1) to (4) in which the first conductor has a region serving as a gate electrode of a transistor, and the transistor has a gate line width of 5 nm or greater and 60 nm or smaller. (6) Another embodiment of the present invention is a method for manufacturing a semiconductor device, including the following steps: forming a first oxide semiconductor over a first insulator; forming a second oxide semiconductor over the first oxide semiconductor; etching part of the first oxide semiconductor and part of the second oxide semiconductor to form an island-shaped oxide semiconductor layer including the first oxide semiconductor and the second oxide semiconductor; forming, over the first insulator and the island-shaped oxide semiconductor layer, a first conductor comprising a first region, a second region, a third region, a fourth region, and a fifth region; forming a resist over the second region, the third region, the fourth region, and the fifth region; etching the first region of the first conductor; reducing the resist to form a resist over the fourth region and the fifth region; etching the first region, the second region, and the third region of the first conductor and then etching the entire first region of the first conductor to form a first conductive layer and a second conductive layer; forming a second conductor over the first insulator, the first conductive layer, and the second conductive layer; forming a second photoresist over the second conductor; etching the second conductor to form a third conductive layer; forming a second insulator over the first insulator and the third conductive layer; forming an opening reaching the top surface of the first insulator and an opening reaching the top surface of the island-shaped oxide semiconductor layer in the second insulator and the third conductive layer to separate the third conductive layer into a fourth conductive layer and a fifth conductive layer; forming a third oxide semiconductor over the second insulator and the island-shaped oxide semiconductor layer; forming a third insulator over the third oxide semiconductor; forming a third conductor over the third insulator; etching part of the third conductor to form a sixth conductive layer; and forming a fourth insulator over the second insulator and the sixth conductive layer. (7) Another embodiment of the present invention is a method for manufacturing a semiconductor device, including the following steps: forming a first oxide semiconductor over a first insulator; forming a second oxide semiconductor over the first oxide semiconductor; etching part of the first oxide semiconductor and part of the second oxide semiconductor to form an island-shaped oxide semiconductor layer including the first oxide semiconductor and the second oxide semiconductor; forming, over the first insulator and the island-shaped oxide semiconductor layer, a first conductor comprising a first region, a second region, a third region, a fourth region, and a fifth region; forming a resist over the second region, the third region, the fourth region, and the fifth region; etching the first region of the first conductor; reducing the resist to form a resist over the fourth region and the fifth region; etching the first region, the second region, and the third region of the first conductor and then etching the entire first region of the first conductor to form a first conductive layer and a second conductive layer; forming a second conductor over the first insulator, the first conductive layer, and the second conductive layer; forming a second photoresist over the second conductor; etching the second conductor to form a third conductive layer; forming a second insulator over the first insulator and the third conductive layer; forming an opening reaching the top surface of the first insulator and an opening reaching the top surface of the island-shaped oxide semiconductor layer in the second insulator and the third conductive layer to separate the third conductive layer into a fourth conductive layer and a fifth conductive layer; forming a third oxide semiconductor over the second insulator and the island-shaped oxide semiconductor layer; forming a third insulator over the third oxide semiconductor; forming a third conductor over the third insulator; etching part of the third conductor to form a sixth conductive layer; forming a fourth insulator over the second insulator and the sixth conductive layer using plasma including oxygen to add the oxygen in the plasma into the second insulator as excess oxygen; performing heat treatment to move the excess oxygen to the second oxide semiconductor; and forming a fifth insulator over the fourth insulator. (8) Another embodiment of the present invention is the method for manufacturing a semiconductor device, according to (6) or (7) in which the third conductive layer is less likely to transmit oxygen than the first conductive layer and the second conductive layer. (9) Another embodiment of the present invention is the method for manufacturing a semiconductor device, according to any one of (6) to (8) in which the third conductive layer is formed to cover the top surface and a side surface of the first conductive layer and the top surface and a side surface of the second conductive layer. (10) Another embodiment of the present invention is the method for manufacturing a semiconductor device, according to any one of (6) to (9), further including the steps of: forming, over the third conductor, a fourth conductor that is less likely to transmit oxygen than the third conductor; forming, below the third conductor, a fifth conductor that is less likely to transmit oxygen than the third conductor; and etching part of the third conductor, part of the fourth conductor, and part of the fifth conductor to form a seventh conductive layer. (11) Another embodiment of the present invention is the method for manufacturing a semiconductor device, according to any one of (6) to (10), further including the step of forming, as the fourth conductor, an insulator that is less likely to transmit oxygen than the first insulator, the second insulator, and the third insulator. (12) Another embodiment of the present invention is the method for manufacturing a semiconductor device, according to any one of (6) to (11), in which the second insulator has a surface planarized by chemical mechanical polishing treatment.

Note that in the semiconductor device of one embodiment of the present invention, the oxide semiconductor may be replaced with another semiconductor.

A miniaturized transistor can be provided. A transistor with low parasitic capacitance can be provided. A transistor with high frequency characteristics can be provided. A transistor with favorable electrical characteristics can be provided. A transistor with stable electrical characteristics can be provided. A transistor with low off-state current can be provided. A novel transistor can be provided. A semiconductor device including the transistor can be provided. A semiconductor device that can operate at high speed can be provided. A novel semiconductor device can be provided. A module including the semiconductor device can be provided. Furthermore, an electronic device including the semiconductor device or the module can be provided.

Note that the description of these effects does not disturb the existence of other effects. One embodiment of the present invention does not necessarily achieve all the effects listed above. Other effects are apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1C are a top view and cross-sectional views illustrating a transistor of one embodiment of the present invention.

FIGS. 2A and 2B are cross-sectional views each illustrating part of a transistor of one embodiment of the present invention.

FIGS. 3A and 3B are cross-sectional views each illustrating part of a transistor of one embodiment of the present invention.

FIGS. 4A and 4B are cross-sectional views each illustrating part of a transistor of one embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating a transistor of one embodiment of the present invention.

FIGS. 6A to 6C are a top view and cross-sectional views illustrating a transistor of one embodiment of the present invention.

FIGS. 7A to 7C are a top view and cross-sectional views illustrating a transistor of one embodiment of the present invention.

FIGS. 8A to 8C are a top view and cross-sectional views illustrating a transistor of one embodiment of the present invention.

FIGS. 9A to 9C are Cs-corrected high-resolution TEM images of a cross section of a CAAC-OS, and FIG. 9D is a cross-sectional schematic view of a CAAC-OS.

FIGS. 10A to 10D are Cs-corrected high-resolution TEM images of a plane of a CAAC-OS.

FIGS. 11A to 11C show structural analysis of a CAAC-OS and a single crystal oxide semiconductor by XRD.

FIGS. 12A and 12B show electron diffraction patterns of a CAAC-OS.

FIG. 13 shows a change in the crystal part of an In—Ga—Zn oxide induced by electron irradiation.

FIGS. 14A to 14C are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 15A to 15C are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 16A to 16C are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 17A to 17C are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 18A to 18C are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 19A to 19C are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 20A to 20C are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 21A to 21C are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 22A to 22C are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 23A to 23C are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 24A to 24D are cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 25A and 25B are cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 26A to 26D are cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 27A to 27D are cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 28A to 28D are cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 29A to 29D are cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 30A and 30B are circuit diagrams of memory devices of one embodiment of the present invention.

FIG. 31 is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention.

FIG. 32 is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention.

FIGS. 33A to 33F are circuit diagrams and cross-sectional views illustrating a semiconductor device of one embodiment of the present invention.

FIG. 34 is a block diagram illustrating a CPU of one embodiment of the present invention.

FIG. 35 is a circuit diagram of a memory element of one embodiment of the present invention.

FIGS. 36A and 36B are plan views of an imaging device.

FIGS. 37A and 37B are plan views of pixels of an imaging device.

FIGS. 38A and 38B are cross-sectional views of an imaging device.

FIGS. 39A and 39B are cross-sectional views of an imaging device.

FIG. 40 illustrates a configuration example of an RF tag.

FIGS. 41A to 41C are a circuit diagram, a top view, and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.

FIGS. 42A and 42B are a circuit diagram and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.

FIG. 43 illustrates a display module.

FIGS. 44A and 44B are perspective views illustrating a cross-sectional structure of a package using a lead frame interposer.

FIGS. 45A to 45E each illustrate an electronic device of one embodiment of the present invention.

FIGS. 46A to 46D are views each illustrating an electronic device according to one embodiment of the present invention.

FIGS. 47A to 47C are views each illustrating an electronic device according to one embodiment of the present invention.

FIGS. 48A to 48F illustrate application examples of an RF tag according to one embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiments of the present invention are described in detail with the reference to the drawings. However, the present invention is not limited to the description below, and it is easily understood by those skilled in the art that embodiments and details disclosed herein can be modified in various ways. Furthermore, the present invention is not construed as being limited to description of the embodiments. In describing structures of the present invention with reference to the drawings, common reference numerals are used for the same portions in different drawings. Note that the same hatched pattern is applied to similar parts, and the similar parts are not especially denoted by reference numerals in some cases.

Note that the size, the thickness of films (layers), or the region in drawings is sometimes exaggerated for simplicity.

In this specification, for example, when the shape of an object is described with use of a term such as “diameter”, “grain size (diameter)”, “dimension”, “size”, or “width”, the term can be regarded as the length of one side of a minimal cube where the object fits, or an equivalent circle diameter of a cross section of the object. The term “equivalent circle diameter of a cross section of the object” refers to the diameter of a perfect circle having the same area as the cross section of the object.

Note that a voltage refers to a potential difference between a certain potential and a reference potential (e.g., a ground potential (GND) or a source potential) in many cases. A voltage can be referred to as a potential and vice versa.

Note that the ordinal numbers such as “first” and “second” in this specification are used for convenience and do not denote the order of steps or the stacking order of layers. Therefore, for example, the term “first” can be replaced with the term “second”, “third”, or the like as appropriate. In addition, the ordinal numbers in this specification and the like are not necessarily the same as those that specify one embodiment of the present invention.

Note that a “semiconductor” includes characteristics of an “insulator” in some cases when the conductivity is sufficiently low, for example. Furthermore, a “semiconductor” and an “insulator” cannot be strictly distinguished from each other in some cases because a border between the “semiconductor” and the “insulator” is not clear. Accordingly, a “semiconductor” in this specification can be called an “insulator” in some cases. Similarly, an “insulator” in this specification can be called a “semiconductor” in some cases.

Furthermore, a “semiconductor” includes characteristics of a “conductor” in some cases when the conductivity is sufficiently high, for example. Furthermore, a “semiconductor” and a “conductor” cannot be strictly distinguished from each other in some cases because a border between the “semiconductor” and the “conductor” is not clear. Accordingly, a “semiconductor” in this specification can be called a “conductor” in some cases. Similarly, a “conductor” in this specification can be called a “semiconductor” in some cases.

Note that an impurity in a semiconductor refers to, for example, elements other than the main components of the semiconductor. For example, an element with a concentration of lower than 0.1 atomic % is an impurity. When an impurity is contained, density of states (DOS) may be formed in the semiconductor, the carrier mobility may be decreased, or the crystallinity may be lowered, for example. In the case where the semiconductor is an oxide semiconductor, examples of an impurity that changes characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components; specifically, there are hydrogen (included in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen, for example. In the case of an oxide semiconductor, oxygen vacancy may be formed by entry of impurities such as hydrogen. Furthermore, in the case where the semiconductor is a silicon film, examples of an impurity that changes characteristics of the semiconductor include oxygen, Group 1 elements except hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements.

Note that the channel length refers to, for example, a distance between a source (a source region or a source electrode) and a drain (a drain region or a drain electrode) in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap with each other or a region where a channel is formed in a top view of the transistor. In one transistor, channel lengths in all regions are not necessarily the same. In other words, the channel length of one transistor is not limited to one value in some cases. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

The channel width refers to, for example, the length of a portion where a source and a drain face each other in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap with each other, or a region where a channel is formed. In one transistor, channel widths in all regions do not necessarily have the same value. In other words, a channel width of one transistor is not fixed to one value in some cases. Therefore, in this specification, a channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

Note that depending on transistor structures, a channel width in a region where a channel is formed actually (hereinafter referred to as an effective channel width) is different from a channel width shown in a top view of a transistor (hereinafter referred to as an apparent channel width) in some cases. For example, in a transistor having a three-dimensional structure, an effective channel width is greater than an apparent channel width shown in a top view of the transistor, and its influence cannot be ignored in some cases. For example, in a miniaturized transistor having a three-dimensional structure, the proportion of a channel region formed in a side surface of a semiconductor is increased in some cases. In that case, an effective channel width obtained when a channel is actually formed is greater than an apparent channel width shown in the top view.

In a transistor having a three-dimensional structure, an effective channel width is difficult to measure in some cases. For example, to estimate an effective channel width from a design value, it is necessary to assume that the shape of a semiconductor is known as an assumption condition. Therefore, in the case where the shape of a semiconductor is not known accurately, it is difficult to measure an effective channel width accurately.

Therefore, in this specification, in a top view of a transistor, an apparent channel width that is a length of a portion where a source and a drain face each other in a region where a semiconductor and a gate electrode overlap with each other is referred to as a surrounded channel width (SCW) in some cases. Furthermore, in this specification, in the case where the term “channel width” is simply used, it may denote a surrounded channel width and an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width in some cases. Note that the values of a channel length, a channel width, an effective channel width, an apparent channel width, a surrounded channel width, and the like can be determined by obtaining and analyzing a cross-sectional TEM image and the like.

Note that in the case where electric field mobility, a current value per channel width, and the like of a transistor are obtained by calculation, a surrounded channel width may be used for the calculation. In that case, a value different from one in the case where an effective channel width is used for the calculation is obtained in some cases.

Note that in this specification, the description “A has a shape jutting out from B” may indicate, for example, the case where at least one of end portions of A is positioned on an outer side of at least one of end portions of B in a top view or a cross-sectional view. Thus, the description “A has a shape jutting out from B” can be read as the description “one end portion of A is positioned on an outer side of one end portion of B in a top view,” for example.

In this specification, the term “parallel” indicates that the angle between two straight lines is greater than or equal to −10° and less than or equal to 10°, and accordingly also includes the case where the angle is greater than or equal to −5° and less than or equal to 5°. The term “perpendicular” indicates that the angle between two straight lines is greater than or equal to 80° and less than or equal to 100°, and accordingly includes the case where the angle is greater than or equal to 85° and less than or equal to 95°.

In this specification, the trigonal and rhombohedral crystal systems are included in the hexagonal crystal system.

Embodiment 1 Transistor Structure 1

A structure of a transistor included in a semiconductor device of one embodiment of the present invention is described below.

FIGS. 1A to 1C are a top view and cross-sectional views of the semiconductor device of one embodiment of the present invention. FIG. 1A is the top view. FIG. 1B is a cross-sectional view taken along dashed-dotted line A1-A2 illustrated in FIG. 1A. FIG. 1C is a cross-sectional view taken along dashed-dotted line A3-A4 illustrated in FIG. 1A. Note that for simplification of the drawing, some components in the top view of FIG. 1A are not illustrated. The arrows in FIGS. 1B and 1C indicate paths through which excess oxygen moves.

The transistor illustrated in FIGS. 1B and 1C includes an insulator 401 over a substrate 400; a conductor 310 over the insulator 401; an insulator 301 that is over the insulator 401 and in contact with the top surface and a side surface of the conductor 310; an insulator 303 over the insulator 301; an insulator 402 over the insulator 303; a semiconductor 406 a over the insulator 402; a semiconductor 406 b over the semiconductor 406 a; a conductor 416 a 1 and a conductor 416 a 2 that are in contact with the top surface and a side surface of the semiconductor 406 b and a side surface of the semiconductor 406 a; a conductor 416 b 1 over the conductor 416 a 1; a conductor 416 b 2 over the conductor 416 a 2; an insulator 410 in contact with the top surface of the conductor 416 b 1 and the top surface of the conductor 416 b 2; a semiconductor 406 c in contact with the top surface of the semiconductor 406 b; an insulator 412 over the semiconductor 406 c; a conductor 404 a over the semiconductor 406 b with the insulator 412 and the semiconductor 406 c interposed therebetween; a conductor 404 b over the conductor 404 a; a conductor 404 c over the conductor 404 b; an insulator 408 that is in contact with the top surface of the insulator 410, the top surface and a side surface of the conductor 404 c, a side surface of the conductor 404 b, a side surface of the conductor 404 a, a side surface of the insulator 412, and a side surface of the semiconductor 406 c; an insulator 428 over the insulator 408; an opening reaching the conductor 404 c through the insulator 428 and the insulator 408; and a conductor 438 embedded in the opening.

Note that the semiconductors 406 a and 406 b include a region 407 where the side surface of the semiconductor 406 a and the top surface and the side surface of the semiconductor 406 b are in contact with the conductors 416 a 1 and 416 a 2.

In the transistor, the conductors 404 a, 404 b, and 404 c serve as a first gate electrode. The conductor 404 a and the conductor 404 c are less likely to transmit oxygen than the conductor 404 b and can prevent a reduction in conductivity caused by oxidization of the conductor 404 b. The insulator 412 serves as a first gate insulator. The conductors 416 a 1 and 416 b 1 and the conductors 416 a 2 and 416 b 2 serve as a source electrode and a drain electrode. The conductors 416 b 1 and 416 b 2 are less likely to transmit oxygen than the conductors 416 a 1 and 416 a 2 and can prevent a reduction in conductivity caused by oxidization of the conductors 416 a 1 and 416 a 2. The resistance of the semiconductor 406 b can be controlled by the potential applied to the conductors 404 a, 404 b, and 404 c. That is, conduction between the conductors 416 a 1 and 416 b 1 and the conductors 416 a 2 and 416 b 2 can be controlled by the potential applied to the conductors 404 a, 404 b, and 404 c.

The conductor 310 functions as a second gate electrode. The conductor 310 can be a multilayer film including a conductive film that is less likely to transmit oxygen. When the conductor 310 is a multilayer film including a conductive film that is less likely to transmit oxygen, a reduction in conductivity caused by oxidization of the conductor 310 can be prevented. The insulators 301, 303, and 402 serve as a second gate insulating film. The potential applied to the conductor 310 can control the threshold voltage of the transistor. Furthermore, the potential applied to the conductor 310 can inject electrons to the insulator 303 and control the threshold voltage of the transistor. When the first gate electrode is electrically connected to the second gate electrode, the current in a conducting state (on-state current) can be increased. Note that the function of the first gate electrode may be interchanged with the function of the second gate electrode.

FIG. 5 illustrates an example in which the first gate electrode is electrically connected to the second gate electrode. A conductor 440 is embedded in an opening reaching the conductor 404 c through the insulators 428 and 408. The top surface of the conductor 440 is electrically connected to the conductor 444 formed over the insulator 428. A conductor 442 is embedded in an opening reaching the conductor 310 through the insulators 428, 408, 410, 402, 303 and 301. The top surface of the conductor 442 is electrically connected to the conductor 444. That is, the conductors 404 a, 404 b, and 404 c serving as the first gate electrode is electrically connected to the conductor 310 serving as the second gate electrode through the conductors 440, 444, and 442.

In the transistor, the conductor 404 a includes a region overlapping with the conductor 416 b 1 with the insulator 412, the semiconductor 406 c, and the insulator 410 provided therebetween, and a region overlapping with the conductor 416 b 2 with the insulator 412, the semiconductor 406 c, and the insulator 410 provided therebetween. Since the transistor includes the insulator 412, the semiconductor 406 c, and the insulator 410 between the conductor 404 a and the conductors 416 b 1 and 416 b 2, parasitic capacitance can be reduced. Thus, the transistor has excellent frequency characteristics.

As illustrated in FIGS. 1B and 1C, the side surfaces of the semiconductors 406 a and 406 b are in contact with the conductors 416 a 1 and 416 a 2. The electric field of the conductors 404 a, 404 b, and 404 c serving as a gate electrode can electrically surround the semiconductors 406 a and 406 b. A structure in which the electric field of a gate electrode electrically surrounds a semiconductor is referred to as a surrounded channel (s-channel) structure. Thus, in some cases, a channel is formed in the entire semiconductor 406 b. In the s-channel structure, a large amount of current can flow between a source and a drain of the transistor, so that current in a conducting state (on-state current) can be increased. In addition, since the electric field of the conductors 404 a, 404 b, and 404 c surround the semiconductors 406 a and 406 b, current in a non-conducting state (off-state current) can be reduced.

In the transistor, the region serving as a gate electrode is formed in a self-aligned manner by filling the openings formed in the insulator 410 and the like; thus, the transistor may be called trench gate self-aligned (TGSA) s-channel FET.

The transistor is surrounded by an insulator having a function of blocking oxygen and impurities such as hydrogen, so that the electronic characteristics of the transistor can be stable. For example, an insulator having a function of blocking oxygen and impurities such as hydrogen is used as the insulators 401 and 408.

An insulator having a function of blocking oxygen and impurities such as hydrogen may have a single-layer structure or a stacked-layer structure including an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum.

For example, the insulator 401 may be formed of aluminum oxide, magnesium oxide, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide. Note that the insulator 401 preferably includes aluminum oxide or silicon nitride. For example, the insulator 401 containing aluminum oxide or silicon nitride can reduce entry of impurities such as hydrogen into the semiconductor 406 b. For another example, the insulator 401 containing aluminum oxide or silicon nitride can reduce outward diffusion of oxygen.

Furthermore, for example, the insulator 408 may be formed of aluminum oxide, magnesium oxide, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide. Note that the insulator 408 preferably contains aluminum oxide. For example, when the insulator 408 is formed by plasma including oxygen, oxygen can be added to the insulator 410 serving as a base layer of the insulator 408. Furthermore, oxygen can also be added to the side surface of the insulator 412. The added oxygen becomes excess oxygen in the insulator 410 or the insulator 412. For example, when the insulator 408 contains aluminum oxide, entry of impurities such as hydrogen into the semiconductor 406 b can be inhibited. For another example, when the insulator 408 contains aluminum oxide, outward diffusion of the excess oxygen added to the insulators 410 and 412 can be reduced.

The insulator 301 may be formed to have, for example, a single-layer structure or a stacked-layer structure including an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. For example, the insulator 301 preferably contains silicon oxide or silicon oxynitride.

The insulator 303 may serve as, for example, an electron-injection layer. The insulator 303 may each be formed to have, for example, a single-layer structure or a stacked-layer structure including an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. For example, the insulator 303 preferably contains silicon nitride, hafnium oxide, or aluminum oxide.

The insulator 402 may be formed to have, for example, a single-layer structure or a stacked-layer structure including an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. For example, the insulator 402 preferably contains silicon oxide or silicon oxynitride.

Note that the insulator 410 preferably includes an insulator with low relative dielectric constant. For example, the insulator 410 preferably contains silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having pores, a resin, or the like. Alternatively, the insulator 410 preferably has a stacked-layer structure of a resin and one of the following materials: silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having pores. When silicon oxide or silicon oxynitride, which is thermally stable, is combined with a resin, the stacked-layer structure can have thermal stability and low relative dielectric constant. Examples of the resin include polyester, polyolefin, polyamide (e.g., nylon or aramid), polyimide, polycarbonate, and acrylic.

The insulator 412 may be formed to have, for example, a single-layer structure or a stacked-layer structure including an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. For example, for the insulator 412, a material containing silicon oxide or silicon oxynitride is preferably used.

Note that the insulator 412 preferably contains an insulator with a high relative dielectric constant. For example, the insulator 412 preferably contains gallium oxide, hafnium oxide, oxide containing aluminum and hafnium, oxynitride containing aluminum and hafnium, oxide containing silicon and hafnium, oxynitride containing silicon and hafnium, or the like. The insulator 412 preferably has a stacked-layer structure containing silicon oxide or silicon oxynitride and an insulator with a high relative dielectric constant. Because silicon oxide and silicon oxynitride have thermal stability, combination of silicon oxide or silicon oxynitride with an insulator with a high relative dielectric constant allows the stacked-layer structure to be thermally stable and have a high relative dielectric constant. For example, when an aluminum oxide, a gallium oxide, or a hafnium oxide of the insulator 412 is on the semiconductor 406 c side, entry of silicon included in the silicon oxide or the silicon oxynitride into the semiconductor 406 b can be suppressed. When silicon oxide or silicon oxynitride is contained on the semiconductor 406 c side, for example, trap centers might be formed at the interface between aluminum oxide, gallium oxide, or hafnium oxide and silicon oxide or silicon oxynitride. The trap centers can shift the threshold voltage of the transistor in the positive direction by trapping electrons in some cases.

The insulator 428 may be formed to have, for example, a single-layer structure or a stacked-layer structure including an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. For example, the insulator 428 may be formed using aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide.

Note that the insulator 428 preferably includes an insulator with low relative dielectric constant. For example, the insulator 428 preferably contains silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having pores, a resin, or the like. Alternatively, the insulator 410 preferably has a stacked-layer structure of a resin and one of the following materials: silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having pores. When silicon oxide or silicon oxynitride, which is thermally stable, is combined with a resin, the stacked-layer structure can have thermal stability and low relative dielectric constant. Examples of the resin include polyester, polyolefin, polyamide (e.g., nylon or aramid), polyimide, polycarbonate, and acrylic.

Each of the conductors 416 a 1, 416 b 1, 416 a 2, and 416 b 2 may be formed to have a single-layer structure or a stacked-layer structure including a conductor containing, for example, one or more kinds of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, platinum, silver, indium, tin, tantalum, and tungsten. For example, an alloy film or a compound film may be used: a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin, and oxygen, a conductor containing titanium and nitrogen, or the like may be used. In particular, tantalum nitride is preferably used because tantalum nitride is less likely to transmit hydrogen and oxygen and is hardly oxidized.

Each of the conductors 404 a, 404 b, and 404 c may be formed to have a single-layer structure or a stacked-layer structure including a conductor containing, for example, one or more kinds of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. For example, an alloy film or a compound film may be used: a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin, and oxygen, a conductor containing titanium and nitrogen, or the like may be used. In particular, tantalum nitride is preferably used because tantalum nitride is less likely to transmit hydrogen and oxygen and is hardly oxidized.

The conductor 438 may be formed to have a single-layer structure or a stacked-layer structure including a conductor containing, for example, one or more kinds of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. For example, an alloy film or a compound film may be used: a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin, and oxygen, a conductor containing titanium and nitrogen, or the like may be used.

Oxide semiconductors are preferably used as the semiconductors 406 a, 406 b, and 406 c. However, silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like can be used in some cases.

FIGS. 2A and 2B are enlarged views of a central portion of the transistor. A gate line width 404 w in FIG. 2A is a length of a region in which the bottom surface of the conductor 404 a, which serves as a gate electrode with the conductors 404 b and 404 c, is parallel to the top surface of the semiconductor 406 b with the insulator 412 and the semiconductor 406 c interposed therebetween. As illustrated in FIG. 2A, the gate line width 404 w of the transistor of one embodiment of the present invention can be smaller than the width of an opening reaching the semiconductor 406 b. That is, the gate line width 404 w can be smaller than the minimum feature size. Specifically, the gate line width 404 w can be 5 nm or greater and 60 nm or smaller, preferably 5 nm or greater and 30 nm or smaller.

Note that when the electric field of the gate electrode is blocked by a conductor provided near the gate electrode, the switching characteristics of the transistor may deteriorate. In the transistor, the positional relation between the conductors 404 a, 404 b, and 404 c serving as a gate electrode and the conductors 416 a 1, 416 b 1, 416 a 2, and 416 b 2 serving as source and drain electrodes depends on the thickness of the insulator 412 serving as a gate insulating film. This change may affect the electrical characteristics of the transistor.

In FIG. 2B, the thickness of a region of the insulator 412 that is between the conductors 416 a 1 and 416 b 1 and the conductors 416 a 2 and 416 b 2 is referred to as a thickness 412 h.

Furthermore, the total thickness of an end portion of the conductor 416 a 1 and an end portion of the conductor 416 b 1 or the total thickness of an end portion of the conductor 416 a 2 and an end portion of the conductor 416 b 2 is referred to as a thickness 416 h.

When the thickness 412 h is smaller than or equal to the thickness 416 h, the electric field of the gate electrode affects the entire channel formation region and thus the switching characteristics of the transistor is improved, which is preferable. The thickness 412 h is 30 nm or smaller, preferably 10 nm or smaller.

The value of the parasitic capacitance formed between the conductors 404 a and 416 b 1 and the value of the parasitic capacitance formed between the conductors 404 a and 416 b 2 are inversely proportional to the thickness of the insulator 410. For example, the parasitic capacitance is negligibly small when the thickness of the insulator 410 is greater than or equal to three times, preferably, five times the thickness of the insulator 412.

One feature of the transistor of one embodiment of the present invention is described here. The conductor 416 a 1 includes a region 416 c and a region 416 d. The region 416 d is thinner than the region 416 c. The conductor 416 a 2 includes a region 416 e and a region 416 f The region 416 e is thinner than the region 416 f The end portion of the region 416 d and the end portion of the region 416 e each have a region facing to the conductor 404 a with the semiconductor 406 c and the insulator 412 interposed therebetween. This facing region can be small. In other words, the thickness 416 h of the portion surrounded by the dotted circle in FIG. 2B can be small. Thus, the value of the parasitic capacitance of the transistor can be small, and the transistor having the structure has high frequency characteristics (see FIG. 2B).

Although the side surfaces of the conductors 404 a, 404 b, and 404 c are aligned with each other in FIGS. 2A and 2B, they are not necessarily aligned with each other. The side surface of the conductor 404 b may recede from the side surfaces of the conductors 404 a and 404 c as illustrated in FIG. 3A. Alternatively, the side surface of the conductor 406 c may recede from the side surface of the insulator 412 as illustrated in FIG. 4A. Further alternatively, the side surfaces of the conductors 404 a and 404 c may recede from the side surface of the conductor 404 b as illustrated in FIG. 4B. The angle between the surface parallel to the substrate and the side surfaces of the conductors 404 a to 404 c is referred to as a taper angle 446 as illustrated in FIG. 3B. The taper angle 446 is greater than or equal to 30° and less than or equal to 95°, preferable greater than or equal to 45° and less than or equal to 90°.

<Transistor Structure 2>

Here, a transistor having a structure different from that in FIGS. 1A to 1C is described with reference to FIGS. 6A to 6C. FIGS. 6A to 6C is a top view and cross-sectional views of the semiconductor device of one embodiment of the present invention. FIG. 6A is the top view. FIG. 6B is a cross-sectional view taken along dashed-dotted line A1-A2 illustrated in FIG. 6A. FIG. 6C is a cross-sectional view taken along dashed-dotted line A3-A4 illustrated in FIG. 6A. Note that for simplification of the drawing, some components in the top view of FIG. 6A are not illustrated.

The transistor illustrated in FIGS. 6B and 6C includes the insulator 401 over the substrate 400; the conductor 310 over the insulator 401; the insulator 301 that is over the insulator 401 and in contact with the top surface and the side surface of the conductor 310; the insulator 303 over the insulator 301; the insulator 402 over the insulator 303; the semiconductor 406 a over the insulator 402; the semiconductor 406 b over the semiconductor 406 a; the conductor 416 a 1 and the conductor 416 a 2 that are in contact with the top surface and the side surface of the semiconductor 406 b and the side surface of the semiconductor 406 a; the conductor 416 b 1 over the conductor 416 a 1; the conductor 416 b 2 over the conductor 416 a 2; the insulator 410 in contact with the top surface of the conductor 416 b 1 and the top surface of the conductor 416 b 2; the semiconductor 406 c in contact with the top surface of the semiconductor 406 b; the insulator 412 over the semiconductor 406 c; the conductor 404 a over the semiconductor 406 b with the insulator 412 and the semiconductor 406 c interposed therebetween; the conductor 404 b over the conductor 404 a; the insulator 408 that is in contact with the top surface of the insulator 410, the side surface of the conductor 404 b, the side surface of the conductor 404 a, the side surface of the insulator 412, and the side surface of the semiconductor 406 c; the insulator 428 over the insulator 408; the opening reaching the conductor 404 b through the insulator 428; and the conductor 438 embedded in the opening.

Note that the semiconductors 406 a and 406 b include the region 407 where the side surface of the semiconductor 406 a and the top surface and the side surface of the semiconductor 406 b are in contact with the conductors 416 a 1 and 416 a 2.

The transistor illustrated in FIGS. 6A to 6C has a different structure from that of the transistor illustrated in FIGS. 1A to 1C in that the insulator 428 has an opening reaching the conductor 404 b not through the insulator 408 and has the conductor 438 embedded in the opening. For other components, refer to the above description.

<Transistor Structure 3>

Here, a transistor having a structure different from that in FIGS. 1A to 1C is described with reference to FIGS. 7A to 7C. FIGS. 7A to 7C is a top view and cross-sectional views of the semiconductor device of one embodiment of the present invention. FIG. 7A is the top view. FIG. 7B is a cross-sectional view taken along dashed-dotted line A1-A2 illustrated in FIG. 7A. FIG. 7C is a cross-sectional view taken along dashed-dotted line A3-A4 illustrated in FIG. 7A. Note that for simplification of the drawing, some components in the top view of FIG. 7A are not illustrated.

The transistor in FIGS. 7A to 7C has a different structure from that of the transistor in FIGS. 1A to 1C in that transistor in FIGS. 7A to 7C includes a plurality of channel formation regions. Although the transistor in FIGS. 7A to 7C includes three channel formation regions, the number of the channel formation regions is not limited to three. For other components, refer to the components of the transistor illustrated in FIGS. 1A to 1C.

<Transistor Structure 4>

Here, a transistor having a structure different from that in FIGS. 1A to 1C is described with reference to FIGS. 8A to 8C. FIGS. 8A to 8C is a top view and cross-sectional views of the semiconductor device of one embodiment of the present invention. FIG. 8A is the top view. FIG. 8B is a cross-sectional view taken along dashed-dotted line A1-A2 illustrated in FIG. 8A. FIG. 8C is a cross-sectional view taken along dashed-dotted line A3-A4 illustrated in FIG. 8A. Note that for simplification of the drawing, some components in the top view of FIG. 8A are not illustrated.

The transistor in FIGS. 8A to 8C is an example of a transistor having a greater channel width than the transistor in FIGS. 1A to 1C. For other components, refer to the components of the transistor illustrated in FIGS. 1A to 1C.

At least part of this embodiment can be implemented in combination with any of the embodiments described in this specification as appropriate.

Embodiment 2 Structure of Oxide Semiconductor

First, a structure of an oxide semiconductor is described below.

An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of a non-single-crystal oxide semiconductor include a c-axis aligned crystalline oxide semiconductor (CAAC-OS), a polycrystalline oxide semiconductor, a nanocrystalline oxide semiconductor (nc-OS), an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor.

From another perspective, an oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.

It is known that an amorphous structure is generally defined as being metastable and unfixed, and being isotropic and having no non-uniform structure. In other words, an amorphous structure has a flexible bond angle and a short-range order but does not have a long-range order.

This means that an inherently stable oxide semiconductor cannot be regarded as a completely amorphous oxide semiconductor. Moreover, an oxide semiconductor that is not isotropic (e.g., an oxide semiconductor that has a periodic structure in a microscopic region) cannot be regarded as a completely amorphous oxide semiconductor. Note that an a-like OS has a periodic structure in a microscopic region, but at the same time has a void and has an unstable structure. For this reason, an a-like OS has physical properties similar to those of an amorphous oxide semiconductor.

<CAAC-OS>

First, a CAAC-OS is described.

A CAAC-OS is one of oxide semiconductors having a plurality of c-axis aligned crystal parts (also referred to as pellets).

In a combined analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of a CAAC-OS, which is obtained using a transmission electron microscope (TEM), a plurality of pellets can be observed. However, in the high-resolution TEM image, a boundary between pellets, that is, a grain boundary is not clearly observed. Thus, in the CAAC-OS, a reduction in electron mobility due to the grain boundary is less likely to occur.

The CAAC-OS observed with a TEM is described below. FIG. 9A shows a high-resolution TEM image of a cross section of the CAAC-OS that is observed from a direction substantially parallel to the sample surface. The high-resolution TEM image is obtained with a spherical aberration corrector function. The high-resolution TEM image obtained with a spherical aberration corrector function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be obtained with, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

FIG. 9B is an enlarged Cs-corrected high-resolution TEM image of a region (1) in FIG. 9A. FIG. 9B shows that metal atoms are arranged in a layered manner in a pellet. Each metal atom layer has a configuration reflecting unevenness of a surface over which the CAAC-OS is formed (hereinafter, the surface is referred to as a formation surface) or the top surface of the CAAC-OS, and is arranged parallel to the formation surface or the top surface of the CAAC-OS.

As shown in FIG. 9B, the CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is denoted by an auxiliary line in FIG. 9C. FIGS. 9B and 9C prove that the size of a pellet is greater than or equal to 1 nm or less than or equal to 3 nm, and the size of a space caused by tilt of the pellets is approximately 0.8 nm. Therefore, the pellet can also be referred to as a nanocrystal (nc). Furthermore, the CAAC-OS can also be referred to as an oxide semiconductor including c-axis aligned nanocrystals (CANC).

Here, according to the Cs-corrected high-resolution TEM images, the schematic arrangement of pellets 5100 of a CAAC-OS over a substrate 5120 is illustrated by such a structure in which bricks or blocks are stacked (see FIG. 9D). The part in which the pellets are tilted as observed in FIG. 9C corresponds to a region 5161 shown in FIG. 9D.

FIG. 10A shows a Cs-corrected high-resolution TEM image of a plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface. FIGS. 10B, 10C, and 10D are enlarged Cs-corrected high-resolution TEM images of regions (1), (2), and (3) in FIG. 10A, respectively. FIGS. 10B, 10C, and 10D indicate that metal atoms are arranged in a triangular, quadrangular, or hexagonal configuration in a pellet. However, there is no regularity of arrangement of metal atoms between different pellets.

Next, a CAAC-OS analyzed by X-ray diffraction (XRD) is described. For example, when the structure of a CAAC-OS including an InGaZnO₄ crystal is analyzed by an out-of-plane method, a peak appears at a diffraction angle (2θ) of around 31° as shown in FIG. 11A. This peak is derived from the (009) plane of the InGaZnO₄ crystal, which indicates that crystals in the CAAC-OS have c-axis alignment, and that the c-axes are aligned in a direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS.

Note that in structural analysis of the CAAC-OS by an out-of-plane method, another peak may appear when 2θ is around 36°, in addition to the peak at 2θ of around 31°. The peak of 2θ at around 36° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS. It is preferable that in the CAAC-OS analyzed by an out-of-plane method, a peak appear when 2θ is around 31° and that a peak not appear when 2θ is around 36°.

On the other hand, in structural analysis of the CAAC-OS by an in-plane method in which an X-ray is incident on a sample in a direction substantially perpendicular to the c-axis, a peak appears when 2θ is around 56°. This peak is derived from the (110) plane of the InGaZnO₄ crystal. In the case of the CAAC-OS, when analysis (φ scan) is performed with 2θ fixed at around 56° and with the sample rotated using a normal vector of the sample surface as an axis (φ axis), as shown in FIG. 11B, a peak is not clearly observed. In contrast, in the case of a single crystal oxide semiconductor of InGaZnO₄, when φ scan is performed with 2θ fixed at around 56°, as shown in FIG. 11C, six peaks that are derived from crystal planes equivalent to the (110) plane are observed. Accordingly, the structural analysis using XRD shows that the directions of a-axes and b-axes are irregularly oriented in the CAAC-OS.

Next, a CAAC-OS analyzed by electron diffraction is described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO₄ crystal in a direction parallel to the sample surface, a diffraction pattern (also referred to as a selected-area transmission electron diffraction pattern) shown in FIG. 12A can be obtained. In this diffraction pattern, spots derived from the (009) plane of an InGaZnO₄ crystal are included. Thus, the electron diffraction also indicates that pellets included in the CAAC-OS have c-axis alignment and that the c-axes are aligned in a direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS. Meanwhile, FIG. 12B shows a diffraction pattern obtained in such a manner that an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. As shown in FIG. 12B, a ring-like diffraction pattern is observed. Thus, the electron diffraction also indicates that the a-axes and b-axes of the pellets included in the CAAC-OS do not have regular alignment. The first ring in FIG. 12B is considered to be derived from the (010) plane, the (100) plane, and the like of the InGaZnO₄ crystal. The second ring in FIG. 12B is considered to be derived from the (110) plane and the like.

As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Entry of impurities, formation of defects, or the like might decrease the crystallinity of an oxide semiconductor. This means that the CAAC-OS has small amounts of impurities and defects (e.g., oxygen vacancies).

Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element (specifically, silicon or the like) having higher strength of bonding to oxygen than a metal element included in an oxide semiconductor extracts oxygen from the oxide semiconductor, which results in disorder of the atomic arrangement and reduced crystallinity of the oxide semiconductor. A heavy metal such as iron or nickel, argon, carbon dioxide, or the like has a large atomic radius (or molecular radius), and thus disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.

The characteristics of an oxide semiconductor having impurities or defects might be changed by light, heat, or the like. Impurities contained in the oxide semiconductor might serve as carrier traps or carrier generation sources, for example. Furthermore, oxygen vacancies in the oxide semiconductor serve as carrier traps or serve as carrier generation sources when hydrogen is captured therein.

The CAAC-OS having small amounts of impurities and oxygen vacancies is an oxide semiconductor with low carrier density (specifically, lower than 8×10¹¹/cm³, preferably lower than 1×10¹¹/cm³, further preferably lower than 1×10¹⁰/cm³, and is higher than or equal to 1×10⁻⁹/cm³). Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. A CAAC-OS has a low impurity concentration and a low density of defect states. Thus, the CAAC-OS can be referred to as an oxide semiconductor having stable characteristics.

<nc-OS>

Next, an nc-OS is described.

An nc-OS has a region in which a crystal part is observed and a region in which a crystal part is not clearly observed in a high-resolution TEM image. In most cases, the size of a crystal part included in the nc-OS film is greater than or equal to 1 nm and less than or equal to 10 nm, or greater than or equal to 1 nm and less than or equal to 3 nm. Note that an oxide semiconductor including a crystal part whose size is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a microcrystalline oxide semiconductor. In a high-resolution TEM image of the nc-OS, for example, a grain boundary is not clearly observed in some cases. Note that there is a possibility that the origin of the nanocrystal is the same as that of a pellet in a CAAC-OS. Therefore, a crystal part of the nc-OS may be referred to as a pellet in the following description.

In the nc-OS, a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. There is no regularity of crystal orientation between different pellets in the nc-OS. Thus, the orientation of the whole film is not observed. Accordingly, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor, depending on an analysis method. For example, when the nc-OS is analyzed by an out-of-plane method using an X-ray beam having a diameter larger than the size of a pellet, a peak that shows a crystal plane does not appear. Furthermore, a diffraction pattern like a halo pattern is observed when the nc-OS is subjected to electron diffraction using an electron beam with a probe diameter (e.g., 50 nm or larger) that is larger than the size of a pellet. Meanwhile, spots appear in a nanobeam electron diffraction pattern of the nc-OS when an electron beam having a probe diameter close to or smaller than the size of a pellet is applied. Moreover, in a nanobeam electron diffraction pattern of the nc-OS, regions with high luminance in a circular (ring) pattern are shown in some cases. Also in a nanobeam electron diffraction pattern of the nc-OS, a plurality of spots is shown in a ring-like region in some cases.

Since there is no regularity of crystal orientation between the pellets (nanocrystals) as mentioned above, the nc-OS can also be referred to as an oxide semiconductor including random aligned nanocrystals (RANC) or an oxide semiconductor including non-aligned nanocrystals (NANC).

Thus, the nc-OS is an oxide semiconductor that has high regularity as compared to an amorphous oxide semiconductor. Therefore, the nc-OS is likely to have a lower density of defect states than an a-like OS and an amorphous oxide semiconductor. Note that there is no regularity of crystal orientation between different pellets in the nc-OS. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

<a-Like OS>

An a-like OS has a structure between those of the nc-OS and the amorphous oxide semiconductor.

In a high-resolution TEM image of the a-like OS film, a void may be observed. Furthermore, in the high-resolution TEM image, there are a region where a crystal part is clearly observed and a region where a crystal part is not observed.

The a-like OS has an unstable structure because it contains a void. To verify that an a-like OS has an unstable structure as compared with a CAAC-OS and an nc-OS, a change in structure caused by electron irradiation is described below.

An a-like OS (referred to as Sample A), an nc-OS (referred to as Sample B), and a CAAC-OS (referred to as Sample C) are prepared as samples subjected to electron irradiation. Each of the samples is an In—Ga—Zn oxide.

First, a high-resolution cross-sectional TEM image of each sample is obtained. The high-resolution cross-sectional TEM images show that all the samples have crystal parts.

Note that which part is regarded as a crystal part is determined as follows. It is known that a unit cell of the InGaZnO₄ crystal has a structure in which nine layers including three In—O layers and six Ga—Zn—O layers are stacked in the c-axis direction. Accordingly, the distance between the adjacent layers is equivalent to the lattice spacing on the (009) plane (also referred to as d value). The value is calculated to be 0.29 nm from crystal structural analysis. Accordingly, a portion where the lattice spacing between lattice fringes is greater than or equal to 0.28 nm and less than or equal to 0.30 nm is regarded as a crystal part of InGaZnO₄. Each of lattice fringes corresponds to the a-b plane of the InGaZnO₄ crystal.

FIG. 13 shows change in the average size of crystal parts (measured in 22 to 45 points) in each sample. Note that the crystal part size corresponds to the length of a lattice fringe. FIG. 13 indicates that the crystal part size in the a-like OS increases with an increase in the cumulative electron dose. Specifically, as shown by (1) in FIG. 13, a crystal part of approximately 1.2 nm (also referred to as an initial nucleus) at the start of TEM observation grows to a size of approximately 2.6 nm at a cumulative electron dose of 4.2×10⁸ e⁻/nm². In contrast, the crystal part size in the nc-OS and the CAAC-OS shows little change from the start of electron irradiation to a cumulative electron dose of 4.2×10⁸ e⁻/nm². Specifically, as shown by (2) and (3) in FIG. 13, the average crystal sizes in an nc-OS and a CAAC-OS are approximately 1.4 nm and approximately 2.1 nm, respectively, regardless of the cumulative electron dose.

In this manner, growth of the crystal part in the a-like OS is induced by electron irradiation. In contrast, in the nc-OS and the CAAC-OS, growth of the crystal part is hardly induced by electron irradiation. Therefore, the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS.

The a-like OS has a lower density than the nc-OS and the CAAC-OS because it contains a void. Specifically, the density of the a-like OS is higher than or equal to 78.6% and lower than 92.3% of the density of the single crystal oxide semiconductor having the same composition. The density of each of the nc-OS and the CAAC-OS is higher than or equal to 92.3% and lower than 100% of the density of the single crystal oxide semiconductor having the same composition. Note that it is difficult to deposit an oxide semiconductor having a density of lower than 78% of the density of the single crystal oxide semiconductor.

For example, in the case of an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of single crystal InGaZnO₄ with a rhombohedral crystal structure is 6.357 g/cm³. Accordingly, in the case of the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of the a-like OS is higher than or equal to 5.0 g/cm³ and lower than 5.9 g/cm³. For example, in the case of the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of each of the nc-OS and the CAAC-OS is higher than or equal to 5.9 g/cm³ and lower than 6.3 g/cm³.

Note that single crystals with the same composition do not exist in some cases. In that case, single crystal oxide semiconductors with different compositions are combined at an adequate ratio, which makes it possible to calculate density equivalent to that of a single crystal oxide semiconductor with the desired composition. The density of a single crystal oxide semiconductor having the desired composition can be calculated using a weighted average according to the combination ratio of the single crystal oxide semiconductors with different compositions. Note that it is preferable to use as few kinds of single crystal oxide semiconductors as possible to calculate the density.

As described above, oxide semiconductors have various structures and various properties. Note that an oxide semiconductor may be a stacked layer including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.

An oxide semiconductor that can be used as the semiconductor 406 a, the semiconductor 406 b, the semiconductor 406 c, or the like is described below.

The semiconductor 406 b is an oxide semiconductor containing indium, for example. An oxide semiconductor can have high carrier mobility (electron mobility) by containing indium, for example. The semiconductor 406 b preferably contains an element M The element M is preferably aluminum, gallium, yttrium, tin, or the like. Other elements that can be used as the element M are boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and the like. Note that two or more of the above elements may be used in combination as the element M The element M is an element having a high bonding energy with oxygen, for example. The element M is an element whose bonding energy with oxygen is higher than that of indium. The element M is an element that can increase the energy gap of the oxide semiconductor, for example. Furthermore, the semiconductor 406 b preferably contains zinc. When the oxide semiconductor contains zinc, the oxide semiconductor is easily to be crystallized, for example.

Note that the semiconductor 406 b is not limited to the oxide semiconductor containing indium. The semiconductor 406 b may be, for example, an oxide semiconductor that does not contain indium and contains zinc, an oxide semiconductor that does not contain indium and contains gallium, or an oxide semiconductor that does not contain indium and contains tin, e.g., a zinc tin oxide, a gallium tin oxide, or gallium oxide.

For the semiconductor 406 b, an oxide with a wide energy gap may be used. For example, the energy gap of the semiconductor 406 b is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.8 eV and less than or equal to 3.8 eV, more preferably greater than or equal to 3 eV and less than or equal to 3.5 eV.

For example, the semiconductor 406 a and the semiconductor 406 c include one or more elements other than oxygen included in the semiconductor 406 b. Since the semiconductor 406 a and the semiconductor 406 c each include one or more elements other than oxygen included in the semiconductor 406 b, an interface state is less likely to be formed at the interface between the semiconductor 406 a and the semiconductor 406 b and the interface between the semiconductor 406 b and the semiconductor 406 c.

The case where the semiconductor 406 a, the semiconductor 406 b, and the semiconductor 406 c contain indium is described. In the case of using an In-M-Zn oxide as the semiconductor 406 a, when the summation of In and M is assumed to be 100 atomic %, the proportions of In and Mare preferably set to be less than 50 atomic % and greater than 50 atomic %, respectively, more preferably less than 25 atomic % and greater than 75 atomic %, respectively. In the case of using an In-M-Zn oxide as the semiconductor 406 b, when the summation of In and M is assumed to be 100 atomic %, the proportions of In and M are preferably set to be greater than 25 atomic % and less than 75 atomic %, respectively, more preferably greater than 34 atomic % and less than 66 atomic %, respectively. In the case of using an In-M-Zn oxide as the semiconductor 406 c, when the summation of In and M is assumed to be 100 atomic %, the proportions of In and M are preferably set to be less than 50 atomic % and greater than 50 atomic %, respectively, more preferably less than 25 atomic % and greater than 75 atomic %, respectively. Note that the semiconductor 406 c may be an oxide that is a type the same as that of the semiconductor 406 a.

As the semiconductor 406 b, an oxide having an electron affinity higher than those of the semiconductors 406 a and 406 c is used. For example, as the semiconductor 406 b, an oxide having an electron affinity higher than those of the semiconductors 406 a and 406 c by 0.07 eV or higher and 1.3 eV or lower, preferably 0.1 eV or higher and 0.7 eV or lower, more preferably 0.15 eV or higher and 0.4 eV or lower is used. Note that the electron affinity refers to an energy gap between the vacuum level and the bottom of the conduction band.

An indium gallium oxide has a small electron affinity and a high oxygen-blocking property. Therefore, the semiconductor 406 c preferably includes an indium gallium oxide. The gallium atomic ratio [Ga/(In+Ga)] is, for example, higher than or equal to 70%, preferably higher than or equal to 80%, more preferably higher than or equal to 90%.

Note that the semiconductor 406 a and/or the semiconductor 406 c may be gallium oxide. For example, when gallium oxide is used for the semiconductor 406 c, a leakage current between the conductor 416 a or 416 b and the conductor 404 a, 404 b or 404 c can be reduced. In other words, the off-state current of the transistor can be reduced.

At this time, when a gate voltage is applied, a channel is formed in the semiconductor 406 b having the highest electron affinity in the semiconductors 406 a, 406 b, and 406 c.

Here, in some cases, there is a mixed region of the semiconductors 406 a and 406 b between the semiconductors 406 a and 406 b. Furthermore, in some cases, there is a mixed region of the semiconductors 406 b and 406 c between the semiconductors 406 b and 406 c. The mixed region has a low density of interface states. For that reason, the stack of the semiconductors 406 a, 406 b, and 406 c has a band diagram where energy at each interface and in the vicinity of the interface is changed continuously (continuous j unction).

At this time, electrons move mainly in the semiconductor 406 b, not in the semiconductor 406 a and the semiconductor 406 c. Thus, when the interface state density at the interface between the semiconductors 406 a and 406 b and the interface state density at the interface between the semiconductors 406 b and 406 c are decreased, electron movement in the semiconductor 406 b is less likely to be inhibited and the on-state current of the transistor can be increased.

In the case where the transistor has an s-channel structure, a channel is formed in the entire semiconductor 406 b. Therefore, as the semiconductor 406 b has a larger thickness, a channel region becomes larger. In other words, the thicker the semiconductor 406 b is, the larger the on-state current of the transistor is. For example, the semiconductor 406 b has a region with a thickness of greater than or equal to 20 nm, preferably greater than or equal to 40 nm, more preferably greater than or equal to 60 nm, still more preferably greater than or equal to 100 nm. Note that if the thickness of semiconductor is too large, the productivity of the semiconductor device including the transistor might be decreased; thus, the semiconductor 406 b has a region with a thickness of, for example, less than or equal to 300 nm, preferably less than or equal to 200 nm, or more preferably less than or equal to 150 nm.

Moreover, the thickness of the semiconductor 406 c is preferably as small as possible to increase the on-state current of the transistor. The semiconductor 406 c has a region with a thickness of less than 10 nm, preferably less than or equal to 5 nm, more preferably less than or equal to 3 nm, for example. Meanwhile, the semiconductor 406 c has a function of blocking entry of elements other than oxygen (such as hydrogen and silicon) included in the adjacent insulator into the semiconductor 406 b where a channel is formed. For this reason, it is preferable that the semiconductor 406 c have a certain thickness. The semiconductor 406 c has a region with a thickness of greater than or equal to 0.3 nm, preferably greater than or equal to 1 nm, more preferably greater than or equal to 2 nm, for example. The semiconductor 406 c preferably has an oxygen blocking property to suppress outward diffusion of oxygen released from the insulator 402 and the like.

To improve reliability, preferably, the thickness of the semiconductor 406 a is large and the thickness of the semiconductor 406 c is small. For example, the semiconductor 406 a has a region with a thickness of greater than or equal to 10 nm, preferably greater than or equal to 20 nm, more preferably greater than or equal to 40 nm, still more preferably greater than or equal to 60 nm. When the thickness of the semiconductor 406 a is made large, a distance from an interface between the adjacent insulator and the semiconductor 406 a to the semiconductor 406 b in which a channel is formed can be large. Since the productivity of the semiconductor device including the transistor might be decreased, the semiconductor 406 a has a region with a thickness, for example, less than or equal to 200 nm, preferably less than or equal to 120 nm, or further preferably less than or equal to 80 nm.

For example, silicon in the oxide semiconductor might serve as a carrier trap or a carrier generation source. Therefore, the silicon concentration of the semiconductor 406 b is preferably as low as possible. For example, a region in which the concentration of silicon measured by secondary ion mass spectrometry (SIMS) is lower than 1×10¹⁹ atoms/cm³, preferably lower than 5×10¹⁸ atoms/cm³, or further preferably lower than 2×10¹⁸ atoms/cm³ is provided between the semiconductors 406 b and 406 a. A region with a silicon concentration measured by SIMS of lower than 1×10¹⁹ atoms/cm³, preferably lower than 5×10¹⁸ atoms/cm³, more preferably lower than 2×10¹⁸ atoms/cm³ is provided between the semiconductors 406 b and 406 c.

It is preferable to reduce the concentration of hydrogen in the semiconductor 406 a and the semiconductor 406 c in order to reduce the concentration of hydrogen in the semiconductor 406 b. The semiconductor 406 a and the semiconductor 406 c each have a region in which the concentration of hydrogen measured by SIMS is lower than or equal to 2×10²⁰ atoms/cm³, preferably lower than or equal to 5×10¹⁹ atoms/cm³, more preferably lower than or equal to 1×10¹⁹ atoms/cm³, still more preferably lower than or equal to 5×10¹⁸ atoms/cm³. It is preferable to reduce the concentration of nitrogen in the semiconductor 406 a and the semiconductor 406 c in order to reduce the concentration of nitrogen in the semiconductor 406 b. The semiconductor 406 a and the semiconductor 406 c each have a region in which the concentration of nitrogen measured by SIMS is lower than 5×10¹⁹ atoms/cm³, preferably lower than or equal to 5×10¹⁸ atoms/cm³, more preferably lower than or equal to 1×10¹⁸ atoms/cm³, still more preferably lower than or equal to 5×10¹⁷ atoms/cm³.

Note that when copper enters the oxide semiconductor, an electron trap might be generated. The electron trap might shift the threshold voltage of the transistor in the positive direction. Therefore, the concentration of copper on the surface of or in the semiconductor 406 b is preferably as low as possible. For example, the semiconductor 406 b preferably has a region in which the copper concentration is lower than or equal to 1×10¹⁹ atoms/cm³, lower than or equal to 5×10¹⁸ atoms/cm³, or lower than or equal to 1×10¹⁸ atoms/cm³.

The above three-layer structure is an example. For example, a two-layer structure without the semiconductor 406 a or the semiconductor 406 c may be employed. A four-layer structure in which any one of the semiconductors described as examples of the semiconductors 406 a, 406, and 406 c is provided below or over the semiconductor 406 a or below or over the semiconductor 406 c may be employed. An n-layer structure (n is an integer of 5 or more) in which any one of the semiconductors described as examples of the semiconductors 406 a, 406 b, and 406 c is provided at two or more of the following positions: over the semiconductor 406 a, below the semiconductor 406 a, over the semiconductor 406 c, and below the semiconductor 406 c may be employed.

As the substrate 400, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used, for example. As the insulator substrate, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (e.g., an yttria-stabilized zirconia substrate), or a resin substrate is used, for example. As the semiconductor substrate, a semiconductor substrate of silicon, germanium, or the like, or a compound semiconductor substrate of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide can be used, for example. A semiconductor substrate in which an insulator region is provided in the above semiconductor substrate, e.g., a silicon on insulator (SOI) substrate or the like is used. As the conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, or the like is used. A substrate including a metal nitride, a substrate including a metal oxide, or the like is used. An insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator, or the like is used. Alternatively, any of these substrates over which an element is provided may be used. As the element provided over the substrate, a capacitor, a resistor, a switching element, a light-emitting element, a memory element, or the like is used.

Alternatively, a flexible substrate may be used as the substrate 400. As a method for providing the transistor over a flexible substrate, there is a method in which the transistor is formed over a non-flexible substrate and then the transistor is separated and transferred to the substrate 400 that is a flexible substrate. In that case, a separation layer is preferably provided between the non-flexible substrate and the transistor. As the substrate 400, a sheet, a film, or a foil containing a fiber may be used. The substrate 400 may have elasticity. The substrate 400 may have a property of returning to its original shape when bending or pulling is stopped. Alternatively, the substrate 400 may have a property of not returning to its original shape. The substrate 400 has a region with a thickness of, for example, greater than or equal to 5 μm and less than or equal to 700 μm, preferably greater than or equal to 10 μm and less than or equal to 500 μm, more preferably greater than or equal to 15 μm and less than or equal to 300 μm. When the substrate 400 has a small thickness, the weight of the semiconductor device including the transistor can be reduced. When the substrate 400 has a small thickness, even in the case of using glass or the like, the substrate 400 may have elasticity or a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device over the substrate 400, which is caused by dropping or the like, can be reduced. That is, a durable semiconductor device can be provided.

For the substrate 400 that is a flexible substrate, metal, an alloy, resin, glass, or fiber thereof can be used, for example. The flexible substrate 400 preferably has a lower coefficient of linear expansion because deformation due to an environment is suppressed. The flexible substrate 400 is formed using, for example, a material whose coefficient of linear expansion is lower than or equal to 1×10⁻³/K, lower than or equal to 5×10⁻⁵/K, or lower than or equal to 1×10⁻⁵/K. Examples of the resin include polyester, polyolefin, polyamide (e.g., nylon or aramid), polyimide, polycarbonate, and acrylic. In particular, aramid is preferably used for the flexible substrate 400 because of its low coefficient of linear expansion.

At least part of this embodiment can be implemented in combination with any of the embodiments described in this specification as appropriate.

Embodiment 3 Method for Manufacturing Transistor Structure 1

A method for manufacturing the transistor illustrated in FIGS. 1A to 1C is described below with reference to FIGS. 14A to 29D.

First, the substrate 400 is prepared.

Next, the insulator 401 is formed. The insulator 401 may be formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

CVD methods can be classified into a plasma enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD) method using heat, a photo CVD method using light, and the like. Moreover, the CVD method can include a metal CVD (MCVD) method and a metal organic CVD (MOCVD) method depending on a source gas.

By using the PECVD method, a high-quality film can be formed at a relatively low temperature. Furthermore, a thermal CVD method does not use plasma and thus causes less plasma damage to an object. For example, a wiring, an electrode, an element (e.g., transistor or capacitor), or the like included in a semiconductor device might be charged up by receiving charges from plasma. In that case, accumulated charges might break the wiring, electrode, element, or the like included in the semiconductor device. By contrast, when a thermal CVD method not using plasma is employed, such plasma damage is not caused and the yield of the semiconductor device can be increased. A thermal CVD method does not cause plasma damage during deposition, so that a film with few defects can be obtained.

An ALD method also causes less plasma damage to an object. An ALD method does not cause plasma damage during deposition, so that a film with few defects can be obtained.

Unlike in a deposition method in which particles ejected from a target or the like are deposited, in a CVD method and an ALD method, a film is formed by reaction at a surface of an object. Thus, a CVD method and an ALD method enable favorable step coverage almost regardless of the shape of an object. In particular, an ALD method enables excellent step coverage and excellent thickness uniformity and can be favorably used for covering a surface of an opening portion with a high aspect ratio, for example. On the other hand, an ALD method has a relatively low deposition rate; thus, it is sometimes preferable to combine an ALD method with another deposition method with a high deposition rate such as a CVD method.

When a CVD method or an ALD method is used, composition of a film to be formed can be controlled with a flow rate ratio of the source gases. For example, by a CVD method or an ALD method, a film with a certain composition can be formed depending on a flow rate ratio of the source gases. Moreover, with a CVD method or an ALD method, by changing the flow rate ratio of the source gases while forming the film, a film whose composition is continuously changed can be formed. In the case where the film is formed while changing the flow rate ratio of the source gases, as compared to the case where the film is formed using a plurality of deposition chambers, time taken for the film formation can be reduced because time taken for transfer and pressure adjustment is omitted.

Next, a conductor is formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like over the insulator 401 and is then processed by a photolithography method or the like to form the conductor 310. The conductor 310 may have a multilayer structure including a conductor that is less likely to transmit oxygen. Next, the insulator 301 is formed over the insulator 401 and the conductor 310. Another method for forming the conductor 310 is described. An insulator to be the insulator 301 is formed over the insulator 401. An opening is formed in the insulator to be the insulator 301, whereby the insulator 301 having the opening is formed. A conductive film to be the conductor 310 is formed over the insulator 301. The conductor 310 may be embedded to the opening in the insulator 301 by chemical mechanical polishing (CMP) or the like.

Then, the insulator 303 is formed over the insulator 301. The insulators 301 and 303 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIGS. 14A to 14C).

The insulator 402 is formed over the insulator 303. The insulator 402 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, treatment to add oxygen to the insulator 402 may be performed. For the treatment to add oxygen, an ion implantation method, a plasma treatment method, or the like can be used. Note that oxygen added to the insulator 402 is excess oxygen.

Next, a semiconductor to be the semiconductor 406 a is formed. The semiconductor to be the semiconductor 406 a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, treatment for adding oxygen to the semiconductor to be the semiconductor 406 a may be performed. For the treatment to add oxygen, an ion implantation method, a plasma treatment method, or the like can be used. Note that oxygen added to the semiconductor to be the semiconductor 406 a is excess oxygen.

When the semiconductor to be the semiconductor 406 a is a stacked-layer film, oxygen is preferably added to a layer of the semiconductor to be the semiconductor 406 a. Then, a semiconductor to be the semiconductor 406 b is formed over the semiconductor to be the semiconductor 406 a.

Next, first heat treatment is preferably performed. The first heat treatment can be performed at a temperature higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 450° C. and lower than or equal to 600° C., further preferably higher than or equal to 520° C. and lower than or equal to 570° C. The first heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The first heat treatment may be performed under a reduced pressure. Alternatively, the first heat treatment may be performed in such a manner that heat treatment is performed in an inert gas atmosphere, and then another heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more in order to compensate desorbed oxygen. By the first heat treatment, crystallinity of the semiconductor can be increased and impurities such as hydrogen and water can be removed, for example.

Next, the semiconductors to be the semiconductors 406 a and 406 b are processed by a photolithography method or the like to form a semiconductor layer including the semiconductors 406 a and 406 b (see FIGS. 15A to 15C). Note that when the semiconductor layer is formed, part of the insulator 402 is also etched and thinned in some cases. That is, the insulator 402 may have a protruding portion in a region in contact with the semiconductor layer.

Next, a conductor is formed. The conductor can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Then, a first resist is formed over the conductor by a photolithography method or the like. First etching is performed by dry etching or the like using the first resist as a mask. Next, second etching is performed. In the second etching, dry etching is performed on the first resist using oxygen plasma or the like to reduce the first resist, so that the second resist is formed. Then, the third etching is performed. In the third etching, the conductor is etched using the second resist as a mask to form the conductors 416 a 1 and 416 a 2 each having a step-like end portion. In the third etching, 20% to 80%, preferably 30% to 60%, of the thickness of the conductor is etched, whereby the end portions of the conductor can be thin. Thus, the area in which the end portions of the conductor face to the gate electrode can be small, which is preferable (see FIGS. 16A to 16C).

Note that the conductors 416 a 1 and 416 a 2 cover the semiconductor layer. The side surface of the semiconductor 406 a and the top surface and the side surface of the semiconductor 406 b are damaged in forming the conductor over the semiconductor layer, and then the region 407 indicated by the dotted line in FIGS. 16B and 16C is formed. The region 407 includes a region of the semiconductors 406 a and 406 b whose resistance is lowered; thus, the contact resistance between the semiconductor 406 b and the conductors 416 a 1 and 416 a 2 can be lowered.

In the photolithography method, first, a resist is exposed to light through a photomask. Next, a region exposed to light is removed or left using a developing solution, so that a resist mask is formed. Then, etching through the resist mask is conducted. As a result, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape. The resist mask is formed by, for example, exposure of the resist to light using KrF excimer laser light, ArF excimer laser light, extreme ultraviolet (EUV) light, or the like. Alternatively, a liquid immersion technique in which a portion between a substrate and a projection lens is filled with liquid (e.g., water) to perform light exposure may be employed. An electron beam or an ion beam may be used instead of the above-mentioned light. Note that a photomask is not necessary in the case of using an electron beam or an ion beam. The resist mask can be removed by dry etching treatment such as ashing, wet etching treatment, wet etching treatment after dry etching treatment, or dry etching treatment after wet etching treatment.

Next, a conductor is formed. The conductor can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The conductor is processed by a photolithography method or the like to form a conductive layer 418 (see FIGS. 17A to 17C).

The insulator 420 is formed. The insulator 420 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Alternatively, the insulator 420 can be formed by a spin coating method, a dipping method, a droplet discharging method (such as an ink-jet method), a printing method (such as screen printing or offset printing), a doctor knife method, a roll coater method, a curtain coater method, or the like (see FIGS. 18A to 18C).

The insulator 420 may be formed to have a flat top surface. For example, the top surface of the insulator 420 may have planarity immediately after the film formation. Alternatively, the insulator 420 may be planarized by removing the insulator 420 from the top surface so that the top surface becomes parallel to a reference surface such as a rear surface of the substrate. Such treatment is referred to as planarization treatment. As the planarization treatment, for example, CMP treatment, dry etching treatment, or the like can be performed. However, the top surface of the insulator 420 is not necessarily flat.

Next, the insulator 420 is processed by the photolithography method or the like, so that the insulator 410 is formed.

Then, the conductive layer 418 is processed and divided into two conductive layers: a conductive layer including the conductors 416 a 1 and 416 b 1 and a conductive layer including the conductors 416 a 2 and 416 b 2 (see FIGS. 19A to 19C). Note that the insulator 410 and the conductive layer 418 may be processed in the same photolithography process. Processing in the same photolithography process can reduce the number of manufacturing steps. Thus, a semiconductor device including the transistor can be manufactured with high productivity. Alternatively, the insulator 410 and the conductive layer 418 may be processed in different photolithography processes. Processing in different photolithography processes may facilitate formation of films with different shapes.

Here, the semiconductor 406 b is exposed. The region 407 of the exposed surface of the semiconductor 406 b is removed by the above-described processing of the conductive layer 418 in some cases. When the processing is performed by a dry etching method, impurity elements such as residual components of the etching gas are attached to the exposed surface of the semiconductor 406 b in some cases. For example, chlorine and the like may be attached when a chlorine-based gas is used as the etching gas. When a hydrocarbon-based gas is used as the etching gas, carbon, hydrogen, and the like may be attached.

The impurity elements attached to the exposed surface of the semiconductor 406 b are preferably reduced. The impurity elements can be reduced by cleaning treatment using dilute hydrofluoric acid, cleaning treatment using ozone, cleaning treatment using ultra violet rays, or the like. Note that some kinds of cleaning treatment may be used in combination. Accordingly, the exposed surface of the semiconductor 406 b, that is, the channel formation region has a high resistance.

In contrast, as already described, the contact resistance value between the semiconductor 406 b and the conductors 416 a 1 and 416 a 2 is low in the region 407 in which the conductors 416 a 1 and 416 a 2 are in contact with the side surface of the semiconductor 406 a and the top surface and the side surface of the semiconductor 406 b; thus, excellent transistor characteristics can be obtained, which is preferable.

Here, a different method for forming the conductors 416 b 1 and 416 b 2 is described.

The same method as the above-described method can be used for the steps up to the formation of the conductors 416 a 1 and 416 a 2 illustrated in FIGS. 16A to 16C.

Next, a conductor to be the conductors 416 b 1 and 416 b 2 is formed. The conductor to be the conductors 416 b 1 and 416 b 2 is processed by a photolithography method or the like to form the conductors 416 b 1 and 416 b 2 (see FIGS. 20A to 20C).

The insulator 420 is formed. The insulator 420 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Alternatively, the insulator 420 can be formed by a spin coating method, a dipping method, a droplet discharging method (such as an ink-jet method), a printing method (such as screen printing or offset printing), a doctor knife method, a roll coater method, a curtain coater method, or the like (see FIGS. 21A to 21C).

The insulator 420 may be formed to have a flat top surface. For example, the top surface of the insulator 420 may have planarity immediately after the film formation. Alternatively, the insulator 420 may be planarized by removing the insulator 420 from the top surface so that the top surface becomes parallel to a reference surface such as a rear surface of the substrate. Such treatment is referred to as planarization treatment. As the planarization treatment, for example, CMP treatment, dry etching treatment, or the like can be performed. However, the top surface of the insulator 420 is not necessarily flat.

Next, the insulator 420 is processed by the photolithography method or the like, so that the insulator 410 is formed. Here, the semiconductor 406 b is exposed. The region 407 of the exposed surface of the semiconductor 406 b is removed by the above-described processing of the conductive layer 418 in some cases. When the processing is performed by a dry etching method, impurity elements such as residual components of the etching gas are attached to the exposed surface of the semiconductor 406 b in some cases. For example, chlorine and the like may be attached when a chlorine-based gas is used as the etching gas. When a hydrocarbon-based gas is used as the etching gas, carbon, hydrogen, and the like may be attached.

The impurity elements attached to the exposed surface of the semiconductor 406 b are preferably reduced. The impurity elements can be reduced by cleaning treatment using dilute hydrofluoric acid cleaning treatment using, ozone, cleaning treatment using ultra violet rays, or the like. Note that some kinds of cleaning treatment may be used in combination. Accordingly, the exposed surface of the semiconductor 406 b, that is, the channel formation region has a high resistance (see FIGS. 22A to 22C).

In contrast, as already described, the contact resistance value between the semiconductor 406 b and the conductors 416 a 1 and 416 a 2 is low in the region 407 in which the conductors 416 a 1 and 416 a 2 are in contact with the side surface of the semiconductor 406 a and the top surface and the side surface of the semiconductor 406 b; thus, excellent transistor characteristics can be obtained, which is preferable.

The following steps for manufacturing the transistor are common in both of the methods.

A semiconductor to be the semiconductor 406 c is formed. An insulator to be the insulator 412 is formed over the semiconductor to be the semiconductor 406 c. The semiconductor to be the semiconductor 406 c and the insulator to be the insulator 412 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The semiconductor to be the semiconductor 406 c and the insulator to be the insulator 412 each should be formed to have a uniform thickness on the side and bottom surface of the opening formed in the insulator 410 and the conductors 416 a 1, 416 b 1, 416 a 2, and 416 b 2. Thus, the ALD method is preferably used.

Then, a conductor to be the conductor 404 a, a conductor to be the conductor 404 b, and a conductor to be the conductor 404 c are formed. The conductors to be the conductors 404 a, 404 b, and 404 c can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The conductors to be the conductors 404 a, 404 b, and 404 c should be formed to fill the opening formed in the insulator 410 and the like. Thus, a CVD method (an MCVD method, in particular) is preferably used. A stacked-layer film of a conductor formed by an ALD method or the like and a conductor formed by an MCVD method is preferred in some cases to increase adhesion between the insulator 412 and the conductor formed by an MCVD method. For example, a stacked-layer film in which titanium nitride and tungsten are formed in this order may be used.

The conductors to be the conductors 404 a, 404 b, and 404 c are processed by a photolithography method or the like to form the gate electrode including the conductors 404 a, 404 b, and 404 c.

Next, the insulator to be the insulator 412 and the semiconductor to be the semiconductor 406 c are processed by a photolithography method or the like to form the insulator 412 and the semiconductor 406 c (see FIGS. 23A to 23C). Note that the conductors 404 a to 404 c may be processed in the same photolithography process as the insulator 412 and the semiconductor 406 c. Processing in the same photolithography process can reduce the number of manufacturing steps. Thus, a semiconductor device including the transistor can be manufactured with high productivity. Alternatively, the conductors 404 a to 404 c may be processed in a photolithography process different from the insulator 412 and the semiconductor 406 c. Processing in different photolithography processes may facilitate formation of films with different shapes. Though the insulator 412 and the semiconductor 406 c are processed in this example, the insulator 412 and the semiconductor 406 c are not necessarily processed in the transistor of one embodiment of the present invention.

For example, FIGS. 27A and 27B illustrate an example in which the insulator 412 and the semiconductor 406 c are not processed. FIGS. 27C and 27D illustrate an example in which the insulator 412 and the semiconductor 406 c are processed in a photolithography process different from that for the conductors 404 a to 404 c. FIGS. 28A and 28B illustrate an example in which the semiconductor 406 c is not processed. FIGS. 28C and 28D illustrate an example in which the insulator 412 is not processed. FIGS. 29A and 29B illustrate an example in which the semiconductor 406 c is processed in a photolithography process different from that for the conductors 404 a to 404 c and the insulator 412. FIGS. 29C and 29D illustrate an example in which the insulator 412 is processed in a photolithography process different from that for the conductors 404 a to 404 c and that for the semiconductor 406 c.

Next, an insulator to be the insulator 408 is formed over the insulator 410 and the gate electrode. The insulator to be the insulator 408 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. To form the insulator to be the insulator 408, aluminum oxide is preferably formed using plasma containing oxygen because oxygen in the plasma can be added as excess oxygen to the top surface of the insulator 410, the side surface of the insulator 412, and the side surface of the semiconductor 406 c. At this time, in some cases, a mixed region 414 containing a large amount of excess oxygen is formed in the vicinity of the interface between the insulator to be the insulator 408 and the insulator 410. FIGS. 24A and 24B illustrate a state in which the excess oxygen is added to the vicinity of the mixed region 414 using arrows. Note that the excess oxygen is denoted by exO (see FIGS. 24A and 24B).

Second heat treatment may be performed at any time after the formation of the insulator to be the insulator 408. By the second heat treatment, the excess oxygen contained in the insulator 410 and the mixed region 414 moves through the insulator 402 and the semiconductor 406 a to the semiconductor 406 b. Furthermore, the excess oxygen contained in the insulator 410 and the mixed region 414 moves through the insulator 412 and/or the semiconductor 406 c to the semiconductor 406 b. The excess oxygen moves to the semiconductor 406 b through the two paths; thus, the defects of the semiconductor 406 b (oxygen vacancies) can be reduced. The paths through which the excess oxygen moves are denoted by arrows in FIGS. 24C and 24D. Note that the excess oxygen is denoted by exO (see FIGS. 24C and 24D).

Note that the second heat treatment may be performed at a temperature such that the excess oxygen (oxygen) contained in the insulator 410 and the mixed region 414 is diffused to the semiconductor 406 b. For example, the description of the first heat treatment may be referred to for the second heat treatment. The second heat treatment is preferably performed at a temperature lower than that of the first heat treatment. The second heat treatment is preferably performed at a temperature lower than that of the first heat treatment by higher than or equal to 20° C. and lower than or equal to 150° C., preferably higher than or equal to 40° C. and lower than or equal to 100° C. Accordingly, superfluous release of the excess oxygen (oxygen) from the insulator 402 can be inhibited. Note that the second heat treatment is not necessarily performed if the heating for forming the layers also serves as the second heat treatment.

Next, an insulator to be the insulator 428 is formed over the insulator 408. The insulator to be the insulator 428 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Then, an opening reaching the conductor 404 b is formed in the insulator to be the insulator 428 and the insulator to be the insulator 408. A conductor is embedded in the opening to form the conductor 438 by photolithography or the like.

Through the above steps, the transistor illustrated in FIGS. 1A to 1C can be manufactured.

FIGS. 25A and 25B illustrate an example of a transistor in which the conductors 416 a 1, 416 b 1, 416 a 2, and 416 b 2 and the insulator 410 are formed by the above-described different method.

A method for manufacturing a transistor having a different structure from the transistor in FIGS. 1A to 1C is described with reference to FIGS. 26A to 26D. The steps up to the formation of the insulator 428 over the insulator 408 are the same as the steps of the above-described method for manufacturing the transistor in FIGS. 1A to 1C (see FIGS. 26A and 26B).

The top surface of the insulator 428 and the conductor 404 c are polished by CMP or the like until the top surface of the conductor 404 b is exposed, whereby an insulating film 458 is formed (see FIGS. 26C and 26D). A conductive film to be the conductor 438 is formed over the conductor 404 b and is processed by a photolithography method or the like, so that the conductor 438 is formed. By this manufacturing method, the conductor 438 serving as a wiring layer can be formed over the top surface of the conductor 404 b serving as a gate electrode without an insulating film having an opening interposed therebetween.

At least part of this embodiment can be implemented in combination with any of the embodiments described in this specification as appropriate.

Embodiment 4 Memory Device 1

An example of a semiconductor device (memory device) that includes the transistor of one embodiment of the present invention, that can retain stored data even when not powered, and that has an unlimited number of write cycles is shown in FIGS. 30A and 30B.

The semiconductor device illustrated in FIG. 30A includes a transistor 3200 using a first semiconductor, a transistor 3300 using a second semiconductor, and a capacitor 3400. Note that any of the above-described transistors can be used as the transistor 3300.

Note that the transistor 3300 is preferably a transistor with a low off-state current. For example, a transistor using an oxide semiconductor can be used as the transistor 3300. Since the off-state current of the transistor 3300 is low, stored data can be retained for a long period at a predetermined node of the semiconductor device. In other words, power consumption of the semiconductor device can be reduced because refresh operation becomes unnecessary or the frequency of refresh operation can be extremely low.

In FIG. 30A, a first wiring 3001 is electrically connected to a source of the transistor 3200. A second wiring 3002 is electrically connected to a drain of the transistor 3200. A third wiring 3003 is electrically connected to one of the source and the drain of the transistor 3300. A fourth wiring 3004 is electrically connected to the gate of the transistor 3300. The gate of the transistor 3200 and the other of the source and the drain of the transistor 3300 are electrically connected to one electrode of the capacitor 3400. A fifth wiring 3005 is electrically connected to the other electrode of the capacitor 3400.

The semiconductor device in FIG. 30A has a feature that the potential of the gate of the transistor 3200 can be retained, and thus enables writing, retaining, and reading of data as follows.

Writing and holding of data are described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned on, so that the transistor 3300 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to a node FG where the gate of the transistor 3200 and the one electrode of the capacitor 3400 are electrically connected to each other. That is, a predetermined charge is supplied to the gate of the transistor 3200 (writing). Here, one of two kinds of charges providing different potential levels (hereinafter referred to as a low-level charge and a high-level charge) is supplied. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off, so that the transistor 3300 is turned off. Thus, the charge is held at the node FG (retaining).

Since the off-state current of the transistor 3300 is low, the charge of the node FG is retained for a long time.

Next, reading of data is described. An appropriate potential (a reading potential) is supplied to the fifth wiring 3005 while a predetermined potential (a constant potential) is supplied to the first wiring 3001, whereby the potential of the second wiring 3002 varies depending on the amount of charge retained in the node FG. This is because in the case of using an n-channel transistor as the transistor 3200, an apparent threshold voltage V_(th) _(_) _(H) at the time when the high-level charge is given to the gate of the transistor 3200 is lower than an apparent threshold voltage V_(th) _(_) _(L) at the time when the low-level charge is given to the gate of the transistor 3200. Here, an apparent threshold voltage refers to the potential of the fifth wiring 3005 that is needed to turn on the transistor 3200. Thus, the potential of the fifth wiring 3005 is set to a potential V₀ that is between V_(th) _(_) _(H) and V_(th) _(_) _(L), whereby charge supplied to the node FG can be determined. For example, in the case where the high-level charge is supplied to the node FG in writing and the potential of the fifth wiring 3005 is V₀ (>V_(th) _(_) _(H)), the transistor 3200 is turned on. On the other hand, in the case where the low-level charge is supplied to the node FG in writing, even when the potential of the fifth wiring 3005 is V₀ (<V_(th) _(_) _(L)), the transistor 3200 remains off. Thus, the data retained in the node FG can be read by determining the potential of the second wiring 3002.

Note that in the case where memory cells are arrayed, it is necessary that data of a desired memory cell is read in read operation. For example, a configuration in which only data of a desired memory cell can be read by supplying a potential at which the transistor 3200 is in “off state” regardless of the electric charge supplied to the node FG, that is, a potential lower than V_(th) _(_) _(H) to the fifth wiring 3005 of memory cells from which data is not read may be employed. For another example, a configuration in which only data of a desired memory cell can be read by supplying a potential at which the transistor 3200 is brought into “on state” regardless of the electric charge supplied to the node FG, that is, a potential higher than V_(th) _(_) _(L) to the fifth wiring 3005 of memory cells from which data is not read may be employed.

<Structure 1 of Semiconductor Device>

FIG. 31 is a cross-sectional view of the semiconductor device of FIG. 30A. The semiconductor device shown in FIG. 31 includes the transistor 3200, the transistor 3300, and the capacitor 3400. The transistor 3300 and the capacitor 3400 are provided over the transistor 3200. Although an example where the transistor shown in FIGS. 1A and 1B is used as the transistor 3300 is shown, a semiconductor device of one embodiment of the present invention is not limited thereto. Therefore, the description regarding the above-mentioned transistors is referred to as appropriate.

The transistor 3200 shown in FIG. 31 is a transistor using a semiconductor substrate 450. The transistor 3200 includes a region 474 a in the semiconductor substrate 450, a region 474 b in the semiconductor substrate 450, an insulator 462, and a conductor 454.

In the transistor 3200, the regions 474 a and 474 b have a function as a source region and a drain region. The insulator 462 has a function as a gate insulator. The conductor 454 has a function as a gate electrode. Therefore, resistance of a channel formation region can be controlled by a potential applied to the conductor 454. In other words, conduction or non-conduction between the region 474 a and the region 474 b can be controlled by the potential applied to the conductor 454.

For the semiconductor substrate 450, a single-material semiconductor substrate of silicon, germanium, or the like or a compound semiconductor substrate of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or the like may be used, for example. A single crystal silicon substrate is preferably used as the semiconductor substrate 450.

For the semiconductor substrate 450, a semiconductor substrate including impurities imparting n-type conductivity is used. However, a semiconductor substrate including impurities imparting p-type conductivity may be used as the semiconductor substrate 450. In that case, a well including impurities imparting the n-type conductivity is provided in a region where the transistor 3200 is formed. Alternatively, the semiconductor substrate 450 may be an i-type semiconductor substrate.

A top surface of the semiconductor substrate 450 preferably has a (110) plane. Then, on-state characteristics of the transistor 3200 can be improved.

The regions 474 a and 474 b are regions including impurities imparting the p-type conductivity. Accordingly, the transistor 3200 has a structure of a p-channel transistor.

Note that although the transistor 3200 is illustrated as a p-channel transistor, the transistor 3200 may be an n-channel transistor.

Note that the transistor 3200 is separated from an adjacent transistor by a region 460 and the like. The region 460 is an insulating region.

The semiconductor device illustrated in FIG. 31 includes an insulator 464, an insulator 466, an insulator 468, an insulator 470, an insulator 472, an insulator 475, an insulator 302, the insulator 303, the insulator 402, the insulator 410, the insulator 408, the insulator 428, an insulator 465, an insulator 467, an insulator 469, an insulator 498, a conductor 480 a, a conductor 480 b, a conductor 480 c, a conductor 478 a, a conductor 478 b, a conductor 478 c, a conductor 476 a, a conductor 476 b, a conductor 476 c, a conductor 479 a, a conductor 479 b, a conductor 479 c, a conductor 477 a, a conductor 477 b, a conductor 477 c, a conductor 484 a, a conductor 484 b, a conductor 484 c, a conductor 484 d, a conductor 482 a, a conductor 482 c, a conductor 483 a, a conductor 483 b, a conductor 483 c, a conductor 483 d, a conductor 485 a, a conductor 485 b, a conductor 485 c, a conductor 485 d, a conductor 487 a, a conductor 487 b, a conductor 487 c, a conductor 488 a, a conductor 488 b, a conductor 488 c, a conductor 490 a, a conductor 490 b, a conductor 489 a, a conductor 489 b, a conductor 491 a, a conductor 491 b, a conductor 491 c, a conductor 492 a, a conductor 492 b, a conductor 492 c, a conductor 494, a conductor 496, the semiconductor 406 a, the semiconductor 406 b, and the semiconductor 406 c.

The insulator 464 is over the transistor 3200. The insulator 466 is over the insulator 464. The insulator 468 is over the insulator 466. The insulator 470 is over the insulator 468. The insulator 472 is over the insulator 470. The insulator 475 is over the insulator 472. The transistor 3300 is over the insulator 475. The insulator 408 is over the transistor 3300. The insulator 428 is over the insulator 408. The insulator 465 is over the insulator 428. The capacitor 3400 is over the insulator 465. The insulator 469 is over the capacitor 3400.

The insulator 464 includes an opening reaching the region 474 a, an opening portion reaching the region 474 b, and an opening reaching the conductor 454, in which the conductor 480 a, the conductor 480 b, and the conductor 480 c are embedded, respectively.

In addition, the insulator 466 includes an opening reaching the conductor 480 a, an opening reaching the conductor 480 b, and an opening reaching the conductor 480 c, in which the conductor 478 a, the conductor 478 b, and the conductor 478 c are embedded, respectively.

The insulator 468 includes an opening reaching the conductor 478 a, an opening reaching the conductor 478 b, and an opening reaching the conductor 478 c. In the openings, the conductor 476 a, the conductor 476 b, and the conductor 476 c are embedded.

The conductor 479 a in contact with the conductor 476 a, the conductor 479 b in contact with the conductor 476 b, and the conductor 479 c in contact with the conductor 476 c are included over the insulator 468. The insulator 472 includes an opening reaching the conductor 479 a through the insulator 470, an opening reaching the conductor 479 b through the insulator 470, and an opening reaching the conductor 479 c through the insulator 470. In the openings, the conductor 477 a, the conductor 477 b, and the conductor 477 c are embedded.

Furthermore, the insulator 475 includes an opening overlapping with the channel formation region of the transistor 3300, an opening reaching the conductor 477 a, an opening reaching the conductor 477 b, and an opening reaching the conductor 477 c. In the openings, the conductor 484 a, the conductor 484 b, the conductor 484 c, and the conductor 484 d are embedded.

The conductor 484 d may have a function as a bottom-gate electrode of the transistor 3300. Alternatively, for example, electric characteristics such as the threshold voltage of the transistor 3300 may be controlled by application of a constant potential to the conductor 484 d. Further alternatively, for example, the conductor 484 d and the top gate electrode of the transistor 3300 may be electrically connected to each other. Thus, the on-state current of the transistor 3300 can be increased. A punch-through phenomenon can be suppressed; thus, stable electric characteristics in the saturation region of the transistor 3300 can be obtained.

In addition, the insulator 402 includes an opening reaching the conductor 484 a through the insulators 303 and 302 and an opening reaching the conductor 484 c through the insulators 303 and 302. In the openings, the conductor 482 a and the conductor 482 c are embedded.

The insulator 428 includes an opening reaching a conductor of one of the source electrode and the drain electrode of the transistor 3300 through the insulator 408 and the insulator 410, an opening reaching a conductor of the other of the source electrode and the drain electrode of the transistor 3300 through the insulator 408 and the insulator 410, an opening reaching the conductor 484 b through the insulator 408, the insulator 410, the insulator 402, the insulator 303, and the insulator 302, and an opening reaching a conductor of the gate electrode of the transistor 3300 through the insulator 408. In the openings, the conductor 483 a, the conductor 483 b, the conductor 483 c, and the conductor 483 d are embedded.

The conductor 485 a in contact with the conductor 483 a, the conductor 485 b in contact with the conductor 483 b, the conductor 485 c in contact with the conductor 483 c, and the conductor 485 d in contact with the conductor 483 d are included over the insulator 428. The insulator 465 includes an opening reaching the conductor 485 a, an opening reaching the conductor 485 b, and an opening reaching the conductor 485 c. In the openings, the conductor 487 a, the conductor 487 b, and the conductor 487 c are embedded.

The conductor 488 a in contact with the conductor 487 a, the conductor 488 b in contact with the conductor 487 b, and the conductor 488 c in contact with the conductor 487 c are included over the insulator 465. The insulator 467 includes an opening reaching the conductor 488 a and an opening reaching the conductor 488 b. In the openings, the conductor 490 a and the conductor 490 b are embedded. The conductor 488 c is in contact with the conductor 494 that is one of the electrodes of the capacitor 3400.

The conductor 489 a in contact with the conductor 490 a and the conductor 489 b in contact with the conductor 490 b are included over the insulator 467. The insulator 469 includes an opening reaching the conductor 489 a, an opening reaching the conductor 489 b, an opening reaching the conductor 496 that is the other electrode of the capacitor 3400. In the openings, the conductors 491 a, 492 b, and 492 c are embedded.

The conductor 492 a in contact with the conductor 491 a, the conductor 492 b in contact with the conductor 491 b, and the conductor 492 c in contact with the conductor 491 c are over the insulator 469.

The insulators 464, 466, 468, 470, 472, 475, 302, 303, 402, 410, 408, 428, 465, 467, 469, and 498 may each be formed to have, for example, a single-layer structure or a stacked-layer structure including an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. The insulator 401 may be formed of, for example, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide.

The insulator that has a function of blocking oxygen and impurities such as hydrogen is preferably included in at least one of the insulators 464, 466, 468, 470, 472, 475, 302, 303, 402, 410, 408, 428, 465, 467, 469, and 498. When an insulator that has a function of blocking oxygen and impurities such as hydrogen is placed near the transistor 3300, the electrical characteristics of the transistor 3300 can be stable.

An insulator with a function of blocking oxygen and impurities such as hydrogen may have a single-layer structure or a stacked-layer structure including an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used.

Each of the conductors 480 a, 480 b, 480 c, 478 a, 478 b, 478 c, 476 a, 476 b, 476 c, 479 a, 479 b, 479 c, 477 a, 477 b, 477 c, 484 a, 484 b, 484 c, 484 d, 482 a, 482 c, 483 a, 483 b, 483 c, 483 d, 485 a, 485 b, 485 c, 485 d, 487 a, 487 b, 487 c, 488 a, 488 b, 488 c, 490 a, 490 b, 489 a, 489 b, 491 a, 491 b, 491 c, 492 a, 492 b, 492 c, 494, and 496 may have a single-layer structure or a stacked-layer structure including a conductor containing, for example, one or more kinds of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. An alloy or a compound may be used, for example, and a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin, and oxygen, a conductor containing titanium and nitrogen, or the like may be used.

Oxide semiconductors are preferably used as the semiconductors 406 a, 406 b, and 406 c. However, silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like can be used in some cases.

The source or drain of the transistor 3200 is electrically connected to the conductor that is one of the source electrode and the drain electrode of the transistor 3300 through the conductors 480 a, 478 a, 476 a, 479 a, 477 a, 484 a, 482 a, and 483 a. The conductor 454 that is the gate electrode of the transistor 3200 is electrically connected to the conductor that is the other of the source electrode and the drain electrode of the transistor 3300 through the conductors 480 c, 478 c, 476 c, 479 c, 477 c, 484 c, 482 c and 483 c.

The capacitor 3400 includes one of the source electrode and the drain electrode of the transistor 3300, the conductor 494 electrically connected to the one of the electrodes of the capacitor 3400 through the conductor 483 c, the conductor 485 c, the conductor 487 c, and the conductor 488 c, the insulator 498, and the conductor 496 that is the other electrode of the capacitor 3400. The capacitor 3400 is preferably formed above or below the transistor 3300 because the semiconductor can be reduced in size.

For the structures of other components, the description of FIGS. 1A and 1B and the like can be referred to as appropriate.

A semiconductor device in FIG. 32 is the same as the semiconductor device in FIG. 31 except the structure of the transistor 3200. Therefore, the description of the semiconductor device in FIG. 31 is referred to for the semiconductor device in FIG. 32. Specifically, in the semiconductor device in FIG. 32, the transistor 3200 is a FIN-type transistor. The effective channel width is increased in the FIN-type transistor 3200, whereby the on-state characteristics of the transistor 3200 can be improved. In addition, since contribution of the electric field of the gate electrode can be increased, the off-state characteristics of the transistor 3200 can be improved. Note that the transistor 3200 may be a p-channel transistor or an n-channel transistor.

<Memory Device 2>

The semiconductor device in FIG. 30B is different from the semiconductor device in FIG. 30A in that the transistor 3200 is not provided. Also in this case, writing and retaining operation of data can be performed in a manner similar to the semiconductor device in FIG. 30A.

Reading of data in the semiconductor device in FIG. 30B is described. When the transistor 3300 is turned on, the third wiring 3003 that is in a floating state and the capacitor 3400 are in the conduction state, and the charge is redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 is changed. The amount of change in potential of the third wiring 3003 varies depending on the potential of the one electrode of the capacitor 3400 (or the charge accumulated in the capacitor 3400).

For example, the potential of the third wiring 3003 after the charge redistribution is (C_(B)×V_(B0)+C×V)/(C_(B)+C), where V is the potential of the one electrode of the capacitor 3400, C is the capacitance of the capacitor 3400, C_(B) is the capacitance component of the third wiring 3003, and V_(B0) is the potential of the third wiring 3003 before the charge redistribution. Thus, it can be found that, assuming that the memory cell is in either of two states in which the potential of the one electrode of the capacitor 3400 is V₁ and V₀ (V₁>V₀), the potential of the third wiring 3003 in the case of the one electrode of the capacitor 3400 retaining the potential V₁ (=(C_(B)×V_(B0)+C×V₁)/(C_(B)+C)) is higher than the potential of the third wiring 3003 in the case of the one electrode of the capacitor 3400 retaining the potential V₀ (=(C_(B)×V_(B0)+C×V₀)/(C_(B)+C)).

Then, by comparing the potential of the third wiring 3003 with a predetermined potential, data can be read.

In this case, a transistor including the first semiconductor may be used for a driver circuit for driving a memory cell, and a transistor including the second semiconductor may be stacked over the driver circuit as the transistor 3300.

When including a transistor using an oxide semiconductor and having a low off-state current, the semiconductor device described above can retain stored data for a long time. In other words, power consumption of the semiconductor device can be reduced because refresh operation becomes unnecessary or the frequency of refresh operation can be extremely low. Moreover, stored data can be retained for a long time even when power is not supplied (note that a potential is preferably fixed).

Furthermore, in the semiconductor device, high voltage is not needed for writing data and deterioration of elements is less likely to occur. Unlike in a conventional nonvolatile memory, for example, it is not necessary to inject and extract electrons into and from a floating gate; thus, a problem such as deterioration of an insulator is not caused. That is, the semiconductor device of one embodiment of the present invention does not have a limit on the number of times of rewriting data, which is a problem of a conventional nonvolatile memory, and the reliability thereof is drastically improved. Furthermore, data is written depending on the state of the transistor (on or off), whereby high-speed operation can be easily achieved. At least part of this embodiment can be implemented in combination with any of the embodiments described in this specification as appropriate.

Embodiment 5 Structure 2 of Semiconductor Device

In this embodiment, an example of a circuit including the transistor of one embodiment of the present invention is described with reference to drawings.

<Cross-Sectional Structure>

FIGS. 33A and 33B are cross-sectional views of a semiconductor device of one embodiment of the present invention. In FIG. 33A, X1-X2 direction represents a channel length direction. In FIG. 33B, Y1-Y2 direction represents a channel width direction. The semiconductor device illustrated in FIGS. 33A and 33B includes a transistor 2200 containing a first semiconductor material in a lower portion and a transistor 2100 containing a second semiconductor material in an upper portion. In FIGS. 33A and 33B, an example is described in which the transistor described above as an example is used as the transistor 2100 containing the second semiconductor material.

Here, the first semiconductor material and the second semiconductor material are preferably materials having different band gaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (examples of such a semiconductor material include silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, and an organic semiconductor), and the second semiconductor material can be an oxide semiconductor. A transistor using a material other than an oxide semiconductor, such as single crystal silicon, can operate at high speed easily. In contrast, a transistor using an oxide semiconductor and described in the above embodiment as an example has excellent subthreshold characteristics and a minute structure. Furthermore, the transistor can operate at a high speed because of its high switching speed and has low leakage current because of its low off-state current.

The transistor 2200 may be either an n-channel transistor or a p-channel transistor, and an appropriate transistor may be used in accordance with a circuit. Furthermore, the specific structure of the semiconductor device, such as the material or the structure used for the semiconductor device, is not necessarily limited to those described here except for the use of the transistor of one embodiment of the present invention that uses an oxide semiconductor.

FIGS. 33A and 33B illustrate a structure in which the transistor 2100 is provided over the transistor 2200 with an insulator 2201, an insulator 2207, and an insulator 2208 provided therebetween. A plurality of wirings 2202 are provided between the transistor 2200 and the transistor 2100. Furthermore, wirings and electrodes provided over and under the insulators are electrically connected to each other through a plurality of plugs 2203 embedded in the insulators. An insulator 2204 covering the transistor 2100 and a wiring 2205 over the insulator 2204 are provided.

The stack of the two kinds of transistors reduces the area occupied by the circuit, allowing a plurality of circuits to be highly integrated.

Here, in the case where a silicon-based semiconductor material is used for the transistor 2200 provided in a lower portion, hydrogen in an insulator provided in the vicinity of the semiconductor film of the transistor 2200 terminates dangling bonds of silicon; accordingly, the reliability of the transistor 2200 can be improved. Meanwhile, in the case where an oxide semiconductor is used for the transistor 2100 provided in an upper portion, hydrogen in an insulator provided in the vicinity of the semiconductor film of the transistor 2100 becomes a factor of generating carriers in the oxide semiconductor; thus, the reliability of the transistor 2100 might be decreased. Therefore, in the case where the transistor 2100 using an oxide semiconductor is provided over the transistor 2200 using a silicon-based semiconductor material, it is particularly effective that the insulator 2207 having a function of preventing diffusion of hydrogen is provided between the transistors 2100 and 2200. The insulator 2207 makes hydrogen remain in the lower portion, thereby improving the reliability of the transistor 2200. In addition, since the insulator 2207 suppresses diffusion of hydrogen from the lower portion to the upper portion, the reliability of the transistor 2100 can also be improved.

The insulator 2207 can be, for example, formed using aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or yttria-stabilized zirconia (YSZ).

Furthermore, a blocking film having a function of preventing diffusion of hydrogen is preferably formed over the transistor 2100 to cover the transistor 2100 including an oxide semiconductor film. For the blocking film, a material that is similar to that of the insulator 2207 can be used, and in particular, an aluminum oxide film is preferably used. During the formation of the aluminum oxide film, excess oxygen can be added to an insulator below the aluminum oxide film. The excess oxygen moves to the oxide semiconductor layer in the transistor 2100 by a heating step to repair defects in the oxide semiconductor layer. Furthermore, the aluminum oxide film has a high shielding (blocking) effect of preventing penetration of both oxygen and impurities such as hydrogen and moisture. Thus, by using the aluminum oxide film as the blocking film covering the transistor 2100, release of oxygen from the oxide semiconductor film included in the transistor 2100 can be prevented and entry of water and hydrogen into the oxide semiconductor film can be prevented. Note that as the blocking film, the insulator 2204 having a stacked-layer structure may be used, or the blocking film may be provided under the insulator 2204.

Note that the transistor 2200 can be a transistor of various types without being limited to a planar type transistor. For example, the transistor 2200 can be a fin-type transistor, a tri-gate transistor, or the like. An example of a cross-sectional view in this case is shown in FIGS. 33E and 33F. An insulator 2212 is provided over a semiconductor substrate 2211. The semiconductor substrate 2211 includes a projecting portion with a thin tip (also referred to a fin). Note that an insulator may be provided over the projecting portion. The insulator functions as a mask for preventing the semiconductor substrate 2211 from being etched when the projecting portion is formed. The projecting portion does not necessarily have the thin tip; a projecting portion with a cuboid-like projecting portion and a projecting portion with a thick tip are permitted, for example. A gate insulator 2214 is provided over the projecting portion of the semiconductor substrate 2211, and a gate electrode 2213 is provided over the gate insulator 2214. Source and drain regions 2215 are formed in the semiconductor substrate 2211. Note that here is shown an example in which the semiconductor substrate 2211 includes the projecting portion; however, a semiconductor device of one embodiment of the present invention is not limited thereto. For example, a semiconductor region having a projecting portion may be formed by processing an SOI substrate.

At least part of this embodiment can be implemented in combination with any of the embodiments described in this specification as appropriate.

Embodiment 6 CMOS Circuit

A circuit diagram in FIG. 33C shows a configuration of a CMOS circuit in which the p-channel transistor 2200 and the n-channel transistor 2100 are connected to each other in series and in which gates of them are connected to each other.

<Analog Switch>

A circuit diagram in FIG. 33D shows a configuration in which sources of the transistors 2100 and 2200 are connected to each other and drains of the transistors 2100 and 2200 are connected to each other. With such a configuration, the transistors can function as a CMOS analog switch. At least part of this embodiment can be implemented in combination with any of the embodiments described in this specification as appropriate.

Embodiment 7 CPU

A CPU that includes the above-described semiconductor device such as the transistor or the memory device is described below.

FIG. 34 is a block diagram illustrating a configuration example of a CPU partly including any of the above-described transistors.

The CPU illustrated in FIG. 34 includes, over a substrate 1190, an arithmetic logic unit (ALU) 1191, an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1198, a rewritable ROM 1199, and a ROM interface 1189. A semiconductor substrate, an SOI substrate, a glass substrate, or the like is used as the substrate 1190. The ROM 1199 and the ROM interface 1189 may be provided over a separate chip. Needless to say, the CPU in FIG. 34 is just an example in which the configuration is simplified, and an actual CPU may have a variety of configurations depending on the application. For example, the CPU may have the following configuration: a structure including the CPU illustrated in FIG. 34 or an arithmetic circuit is considered as one core; a plurality of the cores are included; and the cores operate in parallel. The number of bits that the CPU can process in an internal arithmetic circuit or in a data bus can be 8, 16, 32, or 64, for example.

An instruction that is input to the CPU through the bus interface 1198 is input to the instruction decoder 1193 and decoded therein, and then, input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.

The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 conduct various controls in accordance with the decoded instruction. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. While the CPU is executing a program, the interrupt controller 1194 judges an interrupt request from an external input/output device or a peripheral circuit on the basis of its priority or a mask state, and processes the request. The register controller 1197 generates an address of the register 1196, and reads/writes data from/to the register 1196 in accordance with the state of the CPU.

In the CPU illustrated in FIG. 34, a memory cell is provided in the register 1196. For the memory cell of the register 1196, the above-described transistor, the above-described memory device, or the like can be used.

In the CPU illustrated in FIG. 34, the register controller 1197 selects operation of retaining data in the register 1196 in accordance with an instruction from the ALU 1191. That is, the register controller 1197 selects whether data is retained by a flip-flop or by a capacitor in the memory cell included in the register 1196. When data retaining by the flip-flop is selected, a power supply voltage is supplied to the memory cell in the register 1196. When data retaining by the capacitor is selected, the data is rewritten in the capacitor, and supply of power supply voltage to the memory cell in the register 1196 can be stopped.

FIG. 35 is an example of a circuit diagram of a memory element that can be used as the register 1196. A memory element 1200 includes a circuit 1201 in which stored data is volatile when power supply is stopped, a circuit 1202 in which stored data is nonvolatile even when power supply is stopped, a switch 1203, a switch 1204, a logic element 1206, a capacitor 1207, and a circuit 1220 having a selecting function. The circuit 1202 includes a capacitor 1208, a transistor 1209, and a transistor 1210. Note that the memory element 1200 may further include another element such as a diode, a resistor, or an inductor, as needed.

Here, the above-described memory device can be used as the circuit 1202. When supply of a power supply voltage to the memory element 1200 is stopped, a GND (0 V) or a potential at which the transistor 1209 in the circuit 1202 is turned off continues to be input to a gate of the transistor 1209. For example, a gate of the transistor 1209 is grounded through a load such as a resistor.

Shown here is an example in which the switch 1203 is a transistor 1213 having one conductivity type (e.g., an n-channel transistor) and the switch 1204 is a transistor 1214 having a conductivity type opposite to the one conductivity type (e.g., a p-channel transistor). A first terminal of the switch 1203 corresponds to one of a source and a drain of the transistor 1213, a second terminal of the switch 1203 corresponds to the other of the source and the drain of the transistor 1213, and conduction or non-conduction between the first terminal and the second terminal of the switch 1203 (i.e., the conduction or non-conduction of the transistor 1213) is selected by a control signal RD input to a gate of the transistor 1213. A first terminal of the switch 1204 corresponds to one of a source and a drain of the transistor 1214, a second terminal of the switch 1204 corresponds to the other of the source and the drain of the transistor 1214, and conduction or non-conduction between the first terminal and the second terminal of the switch 1204 (i.e., conduction or non-conduction of the transistor 1214) is selected by the control signal RD input to a gate of the transistor 1214.

One of a source and a drain of the transistor 1209 is electrically connected to one of a pair of electrodes of the capacitor 1208 and a gate of the transistor 1210. Here, the connection portion is referred to as a node M2. One of a source and a drain of the transistor 1210 is electrically connected to a line that can supply a low power supply potential (e.g., a GND line), and the other thereof is electrically connected to the first terminal of the switch 1203 (the one of the source and the drain of the transistor 1213). The second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is electrically connected to the first terminal of the switch 1204 (the one of the source and the drain of the transistor 1214). The second terminal of the switch 1204 (the other of the source and the drain of the transistor 1214) is electrically connected to a line that can supply a power supply potential VDD. The second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213), the first terminal of the switch 1204 (the one of the source and the drain of the transistor 1214), an input terminal of the logic element 1206, and one of a pair of electrodes of the capacitor 1207 are electrically connected to each other. Here, the connection portion is referred to as a node M1. The other of the pair of electrodes of the capacitor 1207 can be supplied with a constant potential. For example, the other of the pair of electrodes of the capacitor 1207 can be supplied with a low power supply potential (e.g., GND) or a high power supply potential (e.g., VDD). The other of the pair of electrodes of the capacitor 1207 is electrically connected to the line that can supply a low power supply potential (e.g., a GND line). The other of the pair of electrodes of the capacitor 1208 can be supplied with a constant potential. For example, the other of the pair of electrodes of the capacitor 1208 can be supplied with a low power supply potential (e.g., GND) or a high power supply potential (e.g., VDD). The other of the pair of electrodes of the capacitor 1208 is electrically connected to the line that can supply a low power supply potential (e.g., a GND line).

The capacitor 1207 and the capacitor 1208 are not necessarily provided as long as the parasitic capacitance of the transistor, the wiring, or the like is actively utilized.

A control signal WE is input to the gate of the transistor 1209. As for each of the switch 1203 and the switch 1204, a conducting state or a non-conducting state between the first terminal and the second terminal is selected by the control signal RD that is different from the control signal WE. When the first terminal and the second terminal of one of the switches are in the conducting state, the first terminal and the second terminal of the other of the switches are in the non-conducting state.

A signal corresponding to data retained in the circuit 1201 is input to the other of the source and the drain of the transistor 1209. FIG. 35 illustrates an example in which a signal output from the circuit 1201 is input to the other of the source and the drain of the transistor 1209. The logic value of a signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is inverted by the logic element 1206, and the inverted signal is input to the circuit 1201 through the circuit 1220.

In the example of FIG. 35, a signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is input to the circuit 1201 through the logic element 1206 and the circuit 1220; however, one embodiment of the present invention is not limited thereto. The signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) may be input to the circuit 1201 without its logic value being inverted. For example, in the case where the circuit 1201 includes a node in which a signal obtained by inversion of the logic value of a signal input from the input terminal is retained, the signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) can be input to the node.

In FIG. 35, the transistors included in the memory element 1200 except for the transistor 1209 can each be a transistor in which a channel is formed in a film formed using a semiconductor other than an oxide semiconductor or in the substrate 1190. For example, the transistor can be a transistor whose channel is formed in a silicon film or a silicon substrate. Alternatively, all the transistors in the memory element 1200 may be a transistor in which a channel is formed in an oxide semiconductor. Further alternatively, in the memory element 1200, a transistor in which a channel is formed in an oxide semiconductor can be included besides the transistor 1209, and a transistor in which a channel is formed in a layer including a semiconductor other than an oxide semiconductor or the substrate 1190 can be used for the reset of the transistors.

As the circuit 1201 in FIG. 35, for example, a flip-flop circuit can be used. As the logic element 1206, for example, an inverter or a clocked inverter can be used.

In a period during which the memory element 1200 is not supplied with the power supply voltage, the semiconductor device of one embodiment of the present invention can retain data stored in the circuit 1201 by the capacitor 1208 that is provided in the circuit 1202.

The off-state current of a transistor in which a channel is formed in an oxide semiconductor is extremely low. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor is significantly lower than that of a transistor in which a channel is formed in silicon having crystallinity. Thus, when the transistor is used as the transistor 1209, a signal held in the capacitor 1208 is retained for a long time also in a period during which the power supply voltage is not supplied to the memory element 1200. The memory element 1200 can accordingly retain the stored content (data) also in a period during which the supply of the power supply voltage is stopped.

Since the above-described memory element performs pre-charge operation with the switch 1203 and the switch 1204, the time required for the circuit 1201 to retain original data again after the supply of the power supply voltage is restarted can be shortened.

In the circuit 1202, a signal retained by the capacitor 1208 is input to the gate of the transistor 1210. Therefore, after supply of the power supply voltage to the memory element 1200 is restarted, the signal retained by the capacitor 1208 can be converted into the one corresponding to the state (the conducting or non-conducting state) of the transistor 1210 to be read from the circuit 1202. Consequently, an original signal can be accurately read even when a potential corresponding to the signal retained by the capacitor 1208 varies to some degree.

By applying the above-described memory element 1200 to a memory device such as a register or a cache memory included in a processor, data in the memory device can be prevented from being lost owing to the stop of the supply of the power supply voltage. Furthermore, shortly after the supply of the power supply voltage is restarted, the memory device can be returned to the same state as that before the power supply is stopped. Therefore, the power supply can be stopped even for a short time in the processor or one or a plurality of logic circuits included in the processor, resulting in lower power consumption.

Although the memory element 1200 is used in a CPU, the memory element 1200 can also be used in an LSI such as a digital signal processor (DSP), a custom LSI, or a programmable logic device (PLD), and a radio frequency (RF) tag.

At least part of this embodiment can be implemented in combination with any of the embodiments described in this specification as appropriate.

Embodiment 8 Imaging Device

FIG. 36A is a top view illustrating an example of an imaging device 200 of one embodiment of the present invention. The imaging device 200 includes a pixel portion 210 and peripheral circuits for driving the pixel portion 210 (a peripheral circuit 260, a peripheral circuit 270, a peripheral circuit 280, and a peripheral circuit 290). The pixel portion 210 includes a plurality of pixels 211 arranged in a matrix with p rows and q columns (p and q are each a natural number greater than or equal to 2). The peripheral circuits 260, 270, 280, and 290 are each connected to a plurality of pixels 211, and a signal for driving the plurality of pixels 211 is supplied. In this specification and the like, in some cases, “a peripheral circuit” or “a driver circuit” indicates all of the peripheral circuits 260, 270, 280, and 290. For example, the peripheral circuit 260 can be regarded as part of the peripheral circuit.

The imaging device 200 preferably includes a light source 291. The light source 291 can emit detection light P1.

The peripheral circuit includes at least one of a logic circuit, a switch, a buffer, an amplifier circuit, and a converter circuit. The peripheral circuit may be provided over a substrate where the pixel portion 210 is formed. A semiconductor device such as an IC chip may be used as part or the whole of the peripheral circuit. Note that as the peripheral circuit, one or more of the peripheral circuits 260, 270, 280, and 290 may be omitted.

As illustrated in FIG. 36B, the pixels 211 may be provided to be inclined in the pixel portion 210 included in the imaging device 200. When the pixels 211 are obliquely arranged, the distance between pixels (pitch) can be shortened in the row direction and the column direction. Accordingly, the quality of an image taken with the imaging device 200 can be improved.

<Configuration Example 1 of Pixel>

The pixel 211 included in the imaging device 200 is formed with a plurality of subpixels 212, and each subpixel 212 is combined with a filter that transmits light with a specific wavelength band (color filter), whereby data for achieving color image display can be obtained.

FIG. 37A is a top view showing an example of the pixel 211 with which a color image is obtained. The pixel 211 illustrated in FIG. 37A includes a subpixel 212 provided with a color filter transmitting light with a red (R) wavelength band (also referred to as a subpixel 212R), a subpixel 212 provided with a color filter transmitting light with a green (G) wavelength band (also referred to as a subpixel 212G), and a subpixel 212 provided with a color filter transmitting light with a blue (B) wavelength band (also referred to as a subpixel 212B). The subpixel 212 can function as a photosensor.

The subpixel 212 (the subpixel 212R, the subpixel 212G, and the subpixel 212B) is electrically connected to a wiring 231, a wiring 247, a wiring 248, a wiring 249, and a wiring 250. In addition, the subpixel 212R, the subpixel 212G, and the subpixel 212B are connected to respective wirings 253 that are independent from one another. In this specification and the like, for example, the wiring 248, the wiring 249, and the wiring 250 that are connected to the pixel 211 in the n-th row (n is an integer greater than or equal to 1 and less than or equal to p) are referred to as a wiring 248[n], and a wiring 249[n], and a wiring 250[n]. For example, the wiring 253 connected to the pixel 211 in the m-th column (m is an integer greater than or equal to 1 and less than or equal to q) is referred to as a wiring 253[m]. Note that in FIG. 37A, the wirings 253 connected to the subpixel 212R, the subpixel 212G, and the subpixel 212B in the pixel 211 in the m-th column are referred to as a wiring 253[m]R, a wiring 253[m]G, and a wiring 253[m]B. The subpixels 212 are electrically connected to the peripheral circuit through the above wirings.

The imaging device 200 has a structure in which the subpixel 212 is electrically connected to the subpixel 212 in an adjacent pixel 211 that is provided with a color filter transmitting light with the same wavelength band as the subpixel 212, via a switch. FIG. 37B shows a connection example of the subpixels 212: the subpixel 212 in the pixel 211 arranged in an n-th row and an m-th column and the subpixel 212 in the adjacent pixel 211 arranged in an (n+1)-th row and the m-th column. In FIG. 37B, the subpixel 212R arranged in the n-th row and the m-th column and the subpixel 212R arranged in the (n+1)-th row and the m-th column are connected to each other via a switch 201. The subpixel 212G arranged in the n-th row and the m-th column and the subpixel 212G arranged in the (n+1)-th row and the m-th column are connected to each other via a switch 202. The subpixel 212B arranged in the n-th row and the m-th column and the subpixel 212B arranged in the (n+1)-th row and the m-th column are connected to each other via a switch 203.

The color filter used in the subpixel 212 is not limited to red (R), green (G), and blue (B) color filters, and color filters that transmit light of cyan (C), yellow (Y), and magenta (M) may be used. By provision of the subpixels 212 that sense light with three different wavelength bands in one pixel 211, a full-color image can be obtained.

The pixel 211 including the subpixel 212 provided with a color filter transmitting yellow (Y) light may be provided, in addition to the subpixels 212 provided with the color filters transmitting red (R), green (G), and blue (B) light. The pixel 211 including the subpixel 212 provided with a color filter transmitting blue (B) light may be provided, in addition to the subpixels 212 provided with the color filters transmitting cyan (C), yellow (Y), and magenta (M) light. When the subpixels 212 sensing light with four different wavelength bands are provided in one pixel 211, the reproducibility of colors of an obtained image can be increased.

For example, in FIG. 37A, in regard to the subpixel 212 sensing a red wavelength band, the subpixel 212 sensing a green wavelength band, and the subpixel 212 sensing a blue wavelength band, the pixel number ratio (or the light receiving area ratio) thereof is not necessarily 1:1:1. For example, the Bayer arrangement in which the pixel number ratio (the light receiving area ratio) of red to green and blue is 1:2:1 may be employed. Alternatively, the pixel number ratio (the light receiving area ratio) of red to green and blue may be 1:6:1.

Although the number of subpixels 212 provided in the pixel 211 may be one, two or more subpixels are preferably provided. For example, when two or more subpixels 212 sensing the same wavelength band are provided, the redundancy is increased, and the reliability of the imaging device 200 can be increased.

When an infrared (IR) filter that transmits infrared light and absorbs or reflects visible light is used as the filter, the imaging device 200 that senses infrared light can be achieved.

Furthermore, when a neutral density (ND) filter (dark filter) is used, output saturation that occurs when a large amount of light enters a photoelectric conversion element (light-receiving element) can be prevented. With a combination of ND filters with different dimming capabilities, the dynamic range of the imaging device can be increased.

Besides the above-described filter, the pixel 211 may be provided with a lens. An arrangement example of the pixel 211, a filter 254, and a lens 255 is described with cross-sectional views in FIGS. 38A and 38B. With the lens 255, the photoelectric conversion element provided in the subpixels 212 can receive incident light efficiently. Specifically, as illustrated in FIG. 38A, light 256 enters a photoelectric conversion element 220 through the lens 255, the filter 254 (a filter 254R, a filter 254G, and a filter 254B), a pixel circuit 230, and the like that are provided in the pixel 211.

However, as indicated by a region surrounded with dashed-dotted lines, part of the light 256 indicated by arrows might be blocked by some wirings 257. Thus, a preferable structure is that the lens 255 and the filter 254 are provided on the photoelectric conversion element 220 side, so that the photoelectric conversion element 220 can efficiently receive the light 256 as illustrated in FIG. 38B. When the light 256 enters the photoelectric conversion element 220 from the photoelectric conversion element 220 side, the imaging device 200 with high sensitivity can be provided.

As the photoelectric conversion element 220 illustrated in FIGS. 38A and 38B, a photoelectric conversion element in which a p-n junction or a p-i-n junction is formed may be used.

The photoelectric conversion element 220 may be formed using a substance that has a function of absorbing a radiation and generating electric charges. Examples of the substance that has a function of absorbing a radiation and generating electric charges include selenium, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, and cadmium zinc alloy.

For example, when selenium is used for the photoelectric conversion element 220, the photoelectric conversion element 220 can have a light absorption coefficient in a wide wavelength range, such as visible light, ultraviolet light, infrared light, X-rays, and gamma rays.

One pixel 211 included in the imaging device 200 may include the subpixel 212 with a first filter in addition to the subpixel 212 illustrated in FIGS. 38A and 38B.

<Configuration Example 2 of Pixel>

An example of a pixel including a transistor using silicon and a transistor using an oxide semiconductor of one embodiment of the present is described below.

FIGS. 39A and 39B are each a cross-sectional view of an element included in an imaging device.

The imaging device illustrated in FIG. 39A includes a transistor 351 including silicon over a silicon substrate 300, transistors 353 and 354 that include an oxide semiconductor and are stacked over the transistor 351, and a photodiode 360 provided in a silicon substrate 300 and including an anode 361 and a cathode 362. The transistors and the photodiode 360 are electrically connected to various plugs 370 and wirings 371. In addition, an anode 361 of the photodiode 360 is electrically connected to the plug 370 through a low-resistance region 363.

The imaging device includes a layer 305 including the transistor 351 provided on the silicon substrate 300 and the photodiode 360 provided in the silicon substrate 300, a layer 320 that is in contact with the layer 305 and includes the wirings 371, a layer 330 that is in contact with the layer 320 and includes the transistors 353 and 354, and a layer 340 that is in contact with the layer 330 and includes a wiring 372 and a wiring 373.

Note that in the example of the cross-sectional view of FIG. 39A, a light-receiving surface of the photodiode 360 is provided on the side opposite to a surface of the silicon substrate 300 where the transistor 351 is formed. With the structure, an optical path can be obtained without the influence by the transistors or wirings, and therefore, a pixel with a high aperture ratio can be formed. Thus, a pixel with a high aperture ratio can be formed. Note that the light-receiving surface of the photodiode 360 can be the same as the surface where the transistor 351 is formed.

In the case where a pixel is formed with use of transistors using an oxide semiconductor, the layer 305 may include the transistor using an oxide semiconductor. Alternatively, the layer 305 may be omitted, and the pixel may include only transistors using an oxide semiconductor.

In addition, in the cross-sectional view of FIG. 39A, the photodiode 360 in the layer 305 and the transistor in the layer 330 can be formed so as to overlap with each other. Thus, the degree of integration of pixels can be increased. In other words, the resolution of the imaging device can be increased.

An imaging device shown in FIG. 39B includes a photodiode 365 in the layer 340 and over the transistor. In FIG. 39B, the layer 305 includes a transistor 352 and the transistor 351 using silicon, the layer 320 includes the wiring 371, the layer 330 includes the transistor 353 and the transistor 354 using an oxide semiconductor layer, and the layer 340 includes the photodiode 365. The photodiode 365 includes a semiconductor layer 366, a semiconductor layer 367, and a semiconductor layer 368, and is electrically connected to the wiring 373 and a wiring 374 through the plug 370.

The element structure shown in FIG. 39B can increase the aperture ratio.

Alternatively, a PIN diode element formed using an amorphous silicon film, a microcrystalline silicon film, or the like may be used as the photodiode 365. In the photodiode 365, an n-type semiconductor layer 368, an i-type semiconductor layer 367, and a p-type semiconductor layer 366 are stacked in this order. The i-type semiconductor layer 367 is preferably formed using amorphous silicon. The p-type semiconductor layer 366 and the n-type semiconductor layer 368 can each be formed using amorphous silicon, microcrystalline silicon, or the like that includes a dopant imparting the corresponding conductivity type. The photodiode 365 in which a photoelectric conversion layer is formed using amorphous silicon has high sensitivity in a visible light wavelength region, and therefore can easily sense weak visible light.

Here, an insulator 380 is provided between the layer 305 including the transistor 351 and the photodiode 360 and the layer 330 including the transistors 353 and 354. However, there is no limitation on the position of the insulator 380.

Hydrogen in an insulator provided in the vicinity of a channel formation region of the transistor 351 terminates dangling bonds of silicon; accordingly, the reliability of the transistor 351 can be improved. In contrast, hydrogen in the insulator provided in the vicinity of the transistor 353, the transistor 354, and the like becomes one of factors generating a carrier in the oxide semiconductor. Thus, the hydrogen may cause a reduction of the reliability of the transistor 353, the transistor 354, and the like. Therefore, in the case where the transistor using an oxide semiconductor is provided over the transistor using a silicon-based semiconductor, it is preferable that the insulator 380 having a function of blocking hydrogen be provided between the transistors. When the hydrogen is confined below the insulator 380, the reliability of the transistor 351 can be improved. In addition, the hydrogen can be prevented from being diffused from a part below the insulator 380 to a part above the insulator 380; thus, the reliability of the transistor 353 and the transistor 354 can be increased. It is preferable to form an insulator 381 over the transistors 353 and 354 because oxygen diffusion can be prevented in the oxide semiconductor.

At least part of this embodiment can be implemented in combination with any of the embodiments described in this specification as appropriate.

Embodiment 9 RF Tag

In this embodiment, an RF tag that includes the transistor described in the above embodiments or the memory device described in the above embodiment is described with reference to FIG. 40.

The RF tag of this embodiment includes a memory circuit, stores necessary data in the memory circuit, and transmits and receives data to/from the outside by using contactless means, for example, wireless communication. With such features, the RF tag can be used for an individual authentication system in which an object or the like is recognized by reading the individual information, for example. Note that the RF tag is required to have extremely high reliability in order to be used for this purpose.

A configuration of the RF tag is described with reference to FIG. 40. FIG. 40 is a block diagram illustrating a configuration example of an RF tag.

As shown in FIG. 40, an RF tag 800 includes an antenna 804 that receives a radio signal 803 that is transmitted from an antenna 802 connected to a communication device 801 (also referred to as an interrogator, a reader/writer, or the like). The RF tag 800 includes a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. A transistor having a rectifying function included in the demodulation circuit 807 may be formed using a material that enables a reverse current to be low enough, for example, an oxide semiconductor. This can suppress the phenomenon of a rectifying function becoming weaker due to generation of a reverse current and prevent saturation of the output from the demodulation circuit. In other words, the input to the demodulation circuit and the output from the demodulation circuit can have a relation closer to a linear relation. Note that data transmission methods are roughly classified into the following three methods: an electromagnetic coupling method in which a pair of coils is provided so as to face each other and communicates with each other by mutual induction, an electromagnetic induction method in which communication is performed using an induction field, and a radio wave method in which communication is performed using a radio wave. Any of these methods can be used in the RF tag 800 described in this embodiment.

Next, the structure of each circuit is described. The antenna 804 exchanges the radio signal 803 with the antenna 802 that is connected to the communication device 801. The rectifier circuit 805 generates an input potential by rectification, for example, half-wave voltage doubler rectification of an input alternating signal generated by reception of a radio signal at the antenna 804 and smoothing of the rectified signal with a capacitor provided in a later stage in the rectifier circuit 805. Note that a limiter circuit may be provided on an input side or an output side of the rectifier circuit 805. The limiter circuit controls electric power so that electric power that is higher than or equal to certain electric power is not input to a circuit in a later stage if the amplitude of the input alternating signal is high and an internal generation voltage is high.

The constant voltage circuit 806 generates a stable power supply voltage from an input potential and supplies it to each circuit. Note that the constant voltage circuit 806 may include a reset signal generation circuit. The reset signal generation circuit is a circuit that generates a reset signal of the logic circuit 809 by utilizing rise of the stable power supply voltage.

The demodulation circuit 807 demodulates the input alternating signal by envelope detection and generates the demodulated signal. Furthermore, the modulation circuit 808 performs modulation in accordance with data to be output from the antenna 804.

The logic circuit 809 analyzes and processes the demodulated signal. The memory circuit 810 holds the input data and includes a row decoder, a column decoder, a memory region, and the like. Furthermore, the ROM 811 stores an identification number (ID) or the like and outputs it in accordance with processing.

Note that the decision whether each circuit described above is provided or not can be made as appropriate as needed.

Here, the memory circuit described in the above embodiment can be used as the memory circuit 810. Since the memory circuit of one embodiment of the present invention can retain data even when not powered, the memory circuit can be favorably used for an RF tag. Furthermore, the memory circuit of one embodiment of the present invention needs power (voltage) needed for data writing significantly lower than that needed in a conventional nonvolatile memory; thus, it is possible to prevent a difference between the maximum communication range in data reading and that in data writing. In addition, it is possible to suppress malfunction or incorrect writing that is caused by power shortage in data writing.

Since the memory circuit of one embodiment of the present invention can be used as a nonvolatile memory, it can also be used as the ROM 811. In this case, it is preferable that a manufacturer separately prepare a command for writing data to the ROM 811 so that a user cannot rewrite data freely. Since the manufacturer gives identification numbers before shipment and then starts shipment of products, instead of putting identification numbers to all the manufactured RF tags, it is possible to put identification numbers to only good products to be shipped. Thus, the identification numbers of the shipped products are in series and customer management corresponding to the shipped products is easily performed.

This embodiment can be combined as appropriate with any of the other embodiments in this specification.

Embodiment 10 Display Device

A display device of one embodiment of the present invention is described below with reference to FIGS. 41A to 41C and FIGS. 42A and 42B.

Examples of a display element provided in the display device include a liquid crystal element (also referred to as a liquid crystal display element) and a light-emitting element (also referred to as a light-emitting display element). The light-emitting element includes, in its category, an element whose luminance is controlled by a current or voltage, and specifically includes, in its category, an inorganic EL element, an organic EL element, and the like. A display device including an EL element (such a display device is also referred to as EL display device) and a display device including a liquid crystal element (such a display device is also referred to as liquid crystal display device) are described below as examples of the display device.

Note that the display device described below includes in its category a panel in which a display element is sealed and a module in which an IC such as a controller is mounted on the panel.

The display device described below refers to an image display device or a light source (including a lighting device). The display device includes any of the following modules: a module provided with a connector such as an FPC or TCP; a module in which a printed wiring board is provided at the end of TCP; and a module in which an integrated circuit (IC) is mounted directly on a display element by a COG method.

FIGS. 41A to 41C show an example of an EL display device according to one embodiment of the present invention. FIG. 41A is a circuit diagram of a pixel in an EL display device. FIG. 41B is a top view showing the whole of the EL display device. FIG. 41C is a cross-sectional view taken along part of dashed-dotted line M-N in FIG. 41B.

FIG. 41A illustrates an example of a circuit diagram of a pixel used in an EL display device.

Note that in this specification and the like, it might be possible for those skilled in the art to constitute one embodiment of the invention even when portions to which all the terminals of an active element (e.g., a transistor or a diode), a passive element (e.g., a capacitor or a resistor), or the like are connected are not specified. In other words, one embodiment of the invention can be clear even when connection portions are not specified. Furthermore, in the case where a connection portion is disclosed in this specification and the like, it can be determined that one embodiment of the invention in which a connection portion is not specified is disclosed in this specification and the like, in some cases. Particularly in the case where the number of portions to which a terminal is connected might be plural, it is not necessary to specify the portions to which the terminal is connected. Therefore, it might be possible to constitute one embodiment of the invention by specifying only portions to which some of terminals of an active element (e.g., a transistor or a diode), a passive element (e.g., a capacitor or a resistor), or the like are connected.

Note that in this specification and the like, it might be possible for those skilled in the art to specify the invention when at least the connection portion of a circuit is specified. Alternatively, it might be possible for those skilled in the art to specify the invention when at least a function of a circuit is specified. In other words, when a function of a circuit is specified, one embodiment of the present invention can be clear. Furthermore, it can be determined that one embodiment of the present invention whose function is specified is disclosed in this specification and the like. Therefore, when a connection portion of a circuit is specified, the circuit is disclosed as one embodiment of the invention even when a function is not specified, and one embodiment of the invention can be constituted. Alternatively, when a function of a circuit is specified, the circuit is disclosed as one embodiment of the invention even when a connection portion is not specified, and one embodiment of the invention can be constituted.

The EL display device illustrated in FIG. 41A includes a switching element 743, a transistor 741, a capacitor 742, and a light-emitting element 719.

Note that FIG. 41A and the like each illustrate an example of a circuit structure; therefore, a transistor can be provided additionally. In contrast, for each node in FIG. 41A and the like, it is possible not to provide an additional transistor, switch, passive element, or the like.

A gate of the transistor 741 is electrically connected to one terminal of the switching element 743 and one electrode of the capacitor 742. A source of the transistor 741 is electrically connected to the other electrode of the capacitor 742 and one electrode of the light-emitting element 719. A drain of the transistor 741 is supplied with a power supply potential VDD. The other terminal of the switching element 743 is electrically connected to a signal line 744. A constant potential is supplied to the other electrode of the light-emitting element 719. The constant potential is a ground potential GND or a potential lower than the ground potential GND.

It is preferable to use a transistor as the switching element 743. When the transistor is used as the switching element, the area of a pixel can be reduced, so that the EL display device can have high resolution. As the switching element 743, a transistor formed through the same step as the transistor 741 can be used, so that EL display devices can be manufactured with high productivity. Note that as the transistor 741 and/or the switching element 743, any of the above-described transistors can be used, for example.

FIG. 41B is a top view of the EL display device. The EL display device includes a substrate 700, a substrate 750, a sealant 734, a driver circuit 735, a driver circuit 736, a pixel 737, and an FPC 732. The sealant 734 is provided between the substrate 700 and the substrate 750 so as to surround the pixel 737, the driver circuit 735, and the driver circuit 736. Note that the driver circuit 735 and/or the driver circuit 736 may be provided outside the sealant 734.

FIG. 41C is a cross-sectional view of the EL display device taken along part of dashed-dotted line M-N in FIG. 41B.

FIG. 41C illustrates a structure of the transistor 741 including an insulator 712 a and a conductor 704 a over the substrate 700; a semiconductor 706 a that is over the insulator 712 a and the conductor 704 a and has a region overlapping with the conductor 704 a; a semiconductor 706 b over the semiconductor 706 a; a conductor 716 a 1 and a conductor 716 a 2 that are in contact with a side surface of the semiconductor 706 a and the top surface and a side surface of the semiconductor 706 b; a conductor 716 b 1 covering the conductor 716 a 1; a conductor 716 b 2 covering the conductor 716 a 2; an insulator 718 a over the conductors 716 b 1 and 716 b 2; a semiconductor 706 c over the semiconductor 706 b; an insulator 718 b over the semiconductor 706 c; a conductor 714 a 3 that is over the insulator 718 b and overlaps with the semiconductor 706 b; a conductor 714 a 2 over the conductor 714 a 3; and a conductor 714 a 1 over the conductor 714 a 2. Note that the structure of the transistor 741 is just an example of the structure of the transistor in FIGS. 1A to 1C that is described in Embodiment 1. The transistor 741 may have a structure different from that illustrated in FIGS. 1A to 1C.

Thus, in the transistor 741 illustrated in FIG. 41C, the conductor 704 a serves as a gate electrode, the insulator 712 a serves as a gate insulator, the conductors 716 a 1 and 716 b 1 serve as a source electrode, the conductors 716 a 2 and 716 b 2 serve as a drain electrode, the insulator 718 b serves as a gate insulator, and the conductors 714 a 1, 714 a 2, and 714 a 3 serve as a gate electrode. Note that in some cases, the electrical characteristics of the semiconductors 706 a to 706 c change by light that enters the semiconductors. To prevent this, it is preferable that one or more of the conductors 704 a, 716 a 1, 716 a 2, 716 b 1, 716 b 2, 714 a 1, 714 a 2, and 714 a 3 have a light-blocking property.

FIG. 41C illustrates a structure of the capacitor 742 including the insulator 712 a and a conductor 704 b over the substrate 700; a conductor 716 a 3 that is over the insulator 712 a and overlaps with the conductor 704 b; a conductor 716 b 3 covering the conductor 716 a 3; the insulator 718 a over the conductor 716 b 3; the semiconductor 706 c over the insulator 718 a; the insulator 718 b over the semiconductor 706 c; a conductor 714 b 3 that is over the insulator 718 b and overlaps with the conductor 716 b 3; a conductor 714 b 2 over the conductor 714 b 3; a conductor 714 b 1 over the conductor 714 b 2; and part of the insulator 718 b is removed in a region where the conductors 716 b 3 and 714 b 3 overlap with each other.

The conductors 714 b 1, 714 b 2, and 714 b 3 serve as one electrode of the capacitor 742. The conductors 716 a 3 and 716 b 3 serve as the other electrode of the capacitor 742.

Thus, the capacitor 742 can be formed using the film of the transistor 741. The conductors 704 a and 704 b are preferably conductors of the same kind, in which case the conductors 704 a and 704 b can be formed through the same step. Furthermore, the conductors 714 a 1, 714 a 2, 714 a 3, 714 b 1, 714 b 2, and 714 b 3 are preferably conductors of the same kind, in which case the conductors 714 a 1, 714 a 2, 714 a 3, 714 b 1, 714 b 2, and 714 b 3 can be formed through the same step.

The capacitor 742 illustrated in FIG. 41C has a large capacitance per area occupied by the capacitor. Therefore, the EL display device illustrated in FIG. 41C has high display quality. Note that although the capacitor 742 illustrated in FIG. 41C has the structure in which the part of the insulator 718 a is removed to reduce the thickness of the region where the conductor 716 b 3 and the conductor 714 b 3 overlap with each other, the structure of the capacitor according to one embodiment of the present invention is not limited to the structure.

An insulator 720 is provided over the transistor 741 and the capacitor 742. Here, the insulator 720 may have an opening portion reaching the conductor 716 b 1 that serves as the source electrode of the transistor 741. A conductor 781 is provided over the insulator 720. The conductor 781 may be electrically connected to the transistor 741 through the opening portion in the insulator 720.

A partition wall 784 having an opening portion reaching the conductor 781 is provided over the conductor 781. A light-emitting layer 782 in contact with the conductor 781 through the opening portion provided in the partition wall 784 is provided over the partition wall 784. A conductor 783 is provided over the light-emitting layer 782. A region where the conductor 781, the light-emitting layer 782, and the conductor 783 overlap with one another serves as the light-emitting element 719. In FIG. 41C, the FPC 732 is connected to a wiring 733 a through a terminal 731. Note that the wiring 733 a may be formed using the same kind of conductor or semiconductor as the conductor or semiconductor included in the transistor 741.

So far, examples of the EL display device are described. Next, an example of a liquid crystal display device is described.

FIG. 42A is a circuit diagram illustrating a configuration example of a pixel of a liquid crystal display device. A pixel shown in FIGS. 42A and 42B includes a transistor 751, a capacitor 752, and an element (liquid crystal element) 753 in which a space between a pair of electrodes is filled with a liquid crystal.

One of a source and a drain of the transistor 751 is electrically connected to a signal line 755, and a gate of the transistor 751 is electrically connected to a scan line 754.

One electrode of the capacitor 752 is electrically connected to the other of the source and the drain of the transistor 751, and the other electrode of the capacitor 752 is electrically connected to a wiring for supplying a common potential.

One electrode of the liquid crystal element 753 is electrically connected to the other of the source and the drain of the transistor 751, and the other electrode of the liquid crystal element 753 is electrically connected to a wiring to which a common potential is supplied. The common potential supplied to the wiring electrically connected to the other electrode of the capacitor 752 may be different from that supplied to the other electrode of the liquid crystal element 753.

Note the description of the liquid crystal display device is made on the assumption that the top view of the liquid crystal display device is similar to that of the EL display device. FIG. 42B is a cross-sectional view of the liquid crystal display device taken along part of dashed-dotted line M-N in FIG. 41B. In FIG. 42B, the FPC 732 is connected to the wiring 733 a via the terminal 731. Note that the wiring 733 a may be formed using the same kind of conductor as the conductor of the transistor 751 or using the same kind of semiconductor as the semiconductor of the transistor 751.

For the transistor 751, the description of the transistor 741 is referred to. For the capacitor 752, the description of the capacitor 742 is referred to. Note that the structure of the capacitor 752 in FIG. 42B corresponds to, but is not limited to, the structure of the capacitor 742 in FIG. 41C.

Note that in the case where an oxide semiconductor is used as the semiconductor of the transistor 751, the off-state current of the transistor 751 can be extremely small. Therefore, an electric charge held in the capacitor 752 is unlikely to leak, so that the voltage applied to the liquid crystal element 753 can be maintained for a long time. Accordingly, the transistor 751 can be kept off during a period in which moving images with few motions or a still image are/is displayed, whereby power for the operation of the transistor 751 can be saved in that period; accordingly a liquid crystal display device with low power consumption can be provided. Furthermore, the area occupied by the capacitor 752 can be reduced; thus, a liquid crystal display device with a high aperture ratio or a high-resolution liquid crystal display device can be provided.

An insulator 721 is provided over the transistor 751 and the capacitor 752. The insulator 721 has an opening portion reaching the transistor 751. A conductor 791 is provided over the insulator 721. The conductor 791 is electrically connected to the transistor 751 through the opening portion in the insulator 721.

An insulator 792 serving as an alignment film is provided over the conductor 791. A liquid crystal layer 793 is provided over the insulator 792. An insulator 794 serving as an alignment film is provided over the liquid crystal layer 793. A spacer 795 is provided over the insulator 794. A conductor 796 is provided over the spacer 795 and the insulator 794. A substrate 797 is provided over the conductor 796.

Owing to the above-described structure, a display device including a capacitor occupying a small area, a display device with high display quality, or a high-resolution display device can be provided.

For example, in this specification and the like, a display element, a display device that is a device including a display element, a light-emitting element, and a light-emitting device that is a device including a light-emitting element can employ various modes or can include various elements. The display element, the display device, the light-emitting element, or the light-emitting device includes at least one of an EL element (e.g., an EL element including organic and inorganic materials, an organic EL element, or an inorganic EL element), an LED (e.g., a white LED, a red LED, a green LED, or a blue LED), a transistor (a transistor that emits light depending on current), an electron emitter, a liquid crystal element, electronic ink, an electrophoretic element, a grating light valve (GLV), a plasma display panel (PDP), a display element using micro electro mechanical systems (MEMS), a digital micromirror device (DMD), a digital micro shutter (DMS), an interferometric modulator display (IMOD) element, a MEMS shutter display element, an optical-interference-type MEMS display element, an electrowetting element, a piezoelectric ceramic display, a display element including a carbon nanotube, and the like. Other than the above, display media whose contrast, luminance, reflectivity, transmittance, or the like is changed by electrical or magnetic effect may be included.

Note that examples of display devices having EL elements include an EL display. Examples of a display device including an electron emitter include a field emission display (FED), an SED-type flat panel display (SED: surface-conduction electron-emitter display), and the like. Examples of display devices including liquid crystal elements include a liquid crystal display (e.g., a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct-view liquid crystal display, or a projection liquid crystal display). Display devices having electronic ink or electrophoretic elements include electronic paper and the like. In the case of a transflective liquid crystal display or a reflective liquid crystal display, some of or all of pixel electrodes function as reflective electrodes. For example, some or all of pixel electrodes are formed to contain aluminum, silver, or the like. In such a case, a memory circuit such as an SRAM can be provided under the reflective electrodes, leading to lower power consumption.

Note that in the case of using an LED, graphene or graphite may be provided under an electrode or a nitride semiconductor of the LED. Graphene or graphite may be a multilayer film in which a plurality of layers are stacked. As described above, provision of graphene or graphite enables easy formation of a nitride semiconductor thereover, such as an n-type GaN semiconductor including crystals. Furthermore, a p-type GaN semiconductor including crystals or the like can be provided thereover, and thus the LED can be formed. Note that an AlN layer may be provided between the n-type GaN semiconductor including crystals and graphene or graphite. The GaN semiconductors included in the LED may be formed by MOCVD. Note that when the graphene is provided, the GaN semiconductors included in the LED can also be formed by a sputtering method.

This embodiment can be combined as appropriate with any of the other embodiments in this specification.

Embodiment 11

In this embodiment, a display module using a semiconductor device of one embodiment of the present invention is described with reference to FIG. 43.

<Display Module>

In a display module 6000 in FIG. 43, a touch panel 6004 connected to an FPC 6003, a display panel 6006 connected to an FPC 6005, a backlight unit 6007, a frame 6009, a printed board 6010, and a battery 6011 are provided between an upper cover 6001 and a lower cover 6002. Note that the backlight unit 6007, the battery 6011, the touch panel 6004, and the like are not provided in some cases.

The semiconductor device of one embodiment of the present invention can be used for, for example, the display panel 6006 and an integrated circuit mounted on a printed circuit board.

The shapes and sizes of the upper cover 6001 and the lower cover 6002 can be changed as appropriate in accordance with the sizes of the touch panel 6004 and the display panel 6006.

The touch panel 6004 can be a resistive touch panel or a capacitive touch panel and may be formed to overlap with the display panel 6006. A counter substrate (sealing substrate) of the display panel 6006 can have a touch panel function. A photosensor may be provided in each pixel of the display panel 6006 so that an optical touch panel function is added. An electrode for a touch sensor may be provided in each pixel of the display panel 6006 so that a capacitive touch panel function is added.

The backlight unit 6007 includes a light source 6008. The light source 6008 may be provided at an end portion of the backlight unit 6007 and a light diffusing plate may be used.

The frame 6009 protects the display panel 6006 and also functions as an electromagnetic shield for blocking electromagnetic waves generated from the printed board 6010. The frame 6009 may function as a radiator plate.

The printed board 6010 has a power supply circuit and a signal processing circuit for outputting a video signal and a clock signal. As a power source for supplying power to the power supply circuit, an external commercial power source or the battery 6011 provided separately may be used. Note that the battery 6011 is not necessary in the case where a commercial power source is used.

The display module 6000 can be additionally provided with a member such as a polarizing plate, a retardation plate, or a prism sheet.

This embodiment can be combined as appropriate with any of the other embodiments in this specification.

Embodiment 12 Package Using a Lead Frame Interposer

FIG. 44A is a perspective view illustrating a cross-sectional structure of a package using a lead frame interposer. In the package illustrated in FIG. 44A, a chip 551 corresponding to the semiconductor device of one embodiment of the present invention is connected to a terminal 552 over an interposer 550 by wire bonding. The terminal 552 is placed on a surface of the interposer 550 on which the chip 551 is mounted. The chip 551 may be sealed by a mold resin 553, in which case the chip 551 is sealed such that part of each of the terminals 552 is exposed.

FIG. 44B illustrates the structure of a module of an electronic device (mobile phone) in which a package is mounted on a circuit board. In the module of the mobile phone in FIG. 44B, a package 602 and a battery 604 are mounted on a printed wiring board 601. The printed wiring board 601 is mounted on a panel 600 including a display element by an FPC 603.

This embodiment can be combined as appropriate with any of the other embodiments in this specification.

Embodiment 13

In this embodiment, electronic devices and lighting devices of one embodiment of the present invention are described with reference to drawings.

<Electronic Device>

Electronic devices and lighting devices can be fabricated using the semiconductor device of one embodiment of the present invention. In addition, highly reliable electronic devices and lighting devices can be fabricated using the semiconductor device of one embodiment of the present invention. Furthermore, electronic devices and lighting devices including touch sensors with improved detection sensitivity can be fabricated using the semiconductor device of one embodiment of the present invention.

Examples of electronic devices are television devices (also referred to as TV or television receivers), monitors for computers and the like, cameras such as digital cameras and digital video cameras, digital photo frames, cellular phones (also referred to as portable telephone devices), portable game machines, portable information terminals, audio playback devices, large game machines such as pin-ball machines, and the like.

In the case of having flexibility, the light-emitting device or lighting device of one embodiment of the present invention can be incorporated along a curved inside/outside wall surface of a house or a building or a curved interior/exterior surface of a car.

Furthermore, the electronic device of one embodiment of the present invention may include a secondary battery. It is preferable that the secondary battery be capable of being charged by non-contact power transmission.

Examples of the secondary battery include a lithium ion secondary battery such as a lithium polymer battery using a gel electrolyte (lithium ion polymer battery), a lithium-ion battery, a nickel-hydride battery, a nickel-cadmium battery, an organic radical battery, a lead-acid battery, an air secondary battery, a nickel-zinc battery, and a silver-zinc battery.

The electronic device of one embodiment of the present invention may include an antenna. When a signal is received by the antenna, the electronic device can display an image, data, or the like on a display portion. When the electronic device includes a secondary battery, the antenna may be used for non-contact power transmission.

FIG. 45A illustrates a portable game machine including a housing 7101, a housing 7102, a display portion 7103, a display portion 7104, a microphone 7105, speakers 7106, an operation key 7107, a stylus 7108, and the like. The semiconductor device of one embodiment of the present invention can be used for an integrated circuit, a CPU, or the like incorporated in the housing 7101. When the light-emitting device of one embodiment of the present invention is used as the display portion 7103 or 7104, it is possible to provide a user-friendly portable game machine with quality that hardly deteriorates. Although the portable game machine illustrated in FIG. 45A includes two display portions, the display portion 7103 and the display portion 7104, the number of display portions included in the portable game machine is not limited to two.

FIG. 45B illustrates a smart watch, which includes a housing 7302, a display portion 7304, operation buttons 7311 and 7312, a connection terminal 7313, a band 7321, a clasp 7322, and the like. The semiconductor device of one embodiment of the present invention can be used for a memory, a CPU, or the like incorporated in the housing 7302.

FIG. 45C illustrates a portable information terminal, which includes a display portion 7502 incorporated in a housing 7501, operation buttons 7503, an external connection port 7504, a speaker 7505, a microphone 7506, and the like. The semiconductor device of one embodiment of the present invention can be used for a memory, a CPU, or the like incorporated in the housing 7501. Note that the display portion 7502 is small- or medium-sized but can perform full high vision, 4 k, or 8 k display because it has greatly high definition; therefore, a significantly clear image can be obtained.

FIG. 45D illustrates a video camera including a first housing 7701, a second housing 7702, a display portion 7703, operation keys 7704, a lens 7705, a joint 7706, and the like. The operation keys 7704 and the lens 7705 are provided for the first housing 7701, and the display portion 7703 is provided for the second housing 7702. The first housing 7701 and the second housing 7702 are connected to each other with the joint 7706, and the angle between the first housing 7701 and the second housing 7702 can be changed with the joint 7706. Images displayed on the display portion 7703 may be switched in accordance with the angle at the joint 7706 between the first housing 7701 and the second housing 7702. The imaging device of one embodiment of the present invention can be used in a portion corresponding to a focus of the lens 7705. The semiconductor device of one embodiment of the present invention can be used for an integrated circuit, a CPU, or the like incorporated in the first housing 7701.

FIG. 45E illustrates a digital signage including a display portion 7902 provided on a utility pole 7901. The semiconductor device of one embodiment of the present invention can be used for a control circuit of the display portion 7902.

FIG. 46A illustrates a notebook personal computer, which includes a housing 8121, a display portion 8122, a keyboard 8123, a pointing device 8124, and the like. The semiconductor device of one embodiment of the present invention can be used for a CPU, a memory, or the like incorporated in the housing 8121. Note that the display portion 8122 is small- or medium-sized but can perform 8 k display because it has greatly high definition; therefore, a significantly clear image can be obtained.

FIG. 46B is an external view of an automobile 9700. FIG. 46C illustrates a driver's seat of the automobile 9700. The automobile 9700 includes a car body 9701, wheels 9702, a dashboard 9703, lights 9704, and the like. The semiconductor device of one embodiment of the present invention can be used in a display portion and a control integrated circuit of the automobile 9700. For example, the display device or input/output device of one embodiment of the present invention can be used in display portions 9710 to 9715 illustrated in FIG. 46C.

The display portion 9710 and the display portion 9711 are display devices or input/output devices provided in an automobile windshield. The display device or input/output device of one embodiment of the present invention can be a see-through display device or input/output device, through which the opposite side can be seen, by using a light-transmitting conductive material for its electrodes. Such a see-through display device or input/output device does not hinder driver's vision during the driving of the automobile 9700. Therefore, the display device or input/output device of one embodiment of the present invention can be provided in the windshield of the automobile 9700. Note that in the case where a transistor or the like for driving the display device or input/output device is provided in the display device or input/output device, a transistor having light-transmitting properties, such as an organic transistor using an organic semiconductor material or a transistor using an oxide semiconductor, is preferably used.

The display portion 9712 is a display device provided on a pillar portion. For example, the display portion 9712 can compensate for the view hindered by the pillar portion by showing an image taken by an imaging unit provided on the car body. The display portion 9713 is a display device provided on a dashboard portion. For example, the display portion 9713 can compensate for the view hindered by the dashboard portion by showing an image taken by an imaging unit provided on the car body. That is, showing an image taken by an imaging unit provided on the outside of the car body leads to elimination of blind areas and enhancement of safety. In addition, showing an image so as to compensate for the area that a driver cannot see makes it possible for the driver to confirm safety easily and comfortably.

FIG. 46D illustrates the inside of a car in which a bench seat is used as a driver seat and a front passenger seat. A display portion 9721 is a display device or input/output device provided in a door portion. For example, the display portion 9721 can compensate for the view hindered by the door portion by showing an image taken by an imaging unit provided on the car body. A display portion 9722 is a display device provided in a steering wheel. A display portion 9723 is a display device provided in the middle of a seating face of the bench seat. Note that the display device can be used as a seat heater by providing the display device on the seating face or backrest and by using heat generated by the display device as a heat source.

The display portion 9714, the display portion 9715, and the display portion 9722 can display a variety of kinds of information such as navigation data, a speedometer, a tachometer, a mileage, a fuel meter, a gearshift indicator, and air-condition setting. The content, layout, or the like of the display on the display portions can be changed freely by a user as appropriate. The information listed above can also be displayed on the display portions 9710 to 9713, 9721, and 9723. The display portions 9710 to 9715 and 9721 to 9723 can also be used as lighting devices. The display portions 9710 to 9715 and 9721 to 9723 can also be used as heating devices.

FIG. 47A illustrates an external view of a camera 8000. The camera 8000 includes a housing 8001, a display portion 8002, an operation button 8003, a shutter button 8004, a connection portion 8005, and the like. A lens 8006 can be put on the camera 8000.

The connection portion 8005 includes an electrode to connect a finder 8100, which is described below, a stroboscope, or the like.

Although the lens 8006 of the camera 8000 here is detachable from the housing 8001 for replacement, the lens 8006 may be included in the housing 8001.

Images can be taken at the press of the shutter button 8004. In addition, images can be taken at the touch of the display portion 8002 that serves as a touch panel.

The display device or input/output device of one embodiment of the present invention can be used in the display portion 8002.

FIG. 47B shows the camera 8000 with the finder 8100 connected.

The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

The housing 8101 includes a connection portion for engagement with the connection portion 8005 of the camera 8000 so that the finder 8100 can be connected to the camera 8000. The connection portion includes an electrode, and an image or the like received from the camera 8000 through the electrode can be displayed on the display portion 8102.

The button 8103 has a function of a power button, and the display portion 8102 can be turned on and off with the button 8103.

The semiconductor device of one embodiment of the present invention can be used for an integrated circuit and an image sensor included in the housing 8101.

Although the camera 8000 and the finder 8100 are separate and detachable electronic devices in FIGS. 47A and 47B, the housing 8001 of the camera 8000 may include a finder having the display device or input/output device of one embodiment of the present invention.

FIG. 47C illustrates an external view of a head-mounted display 8200.

The head-mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, a cable 8205, and the like. The mounting portion 8201 includes a battery 8206.

Power is supplied from the battery 8206 to the main body 8203 through the cable 8205. The main body 8203 includes a wireless receiver or the like to receive video data, such as image data, and display it on the display portion 8204. The movement of the eyeball and the eyelid of a user is captured by a camera in the main body 8203 and then coordinates of the points the user looks at are calculated using the captured data to utilize the eye of the user as an input means.

The mounting portion 8201 may include a plurality of electrodes so as to be in contact with the user. The main body 8203 may be configured to sense current flowing through the electrodes with the movement of the user's eyeball to recognize the direction of his or her eyes. The main body 8203 may be configured to sense current flowing through the electrodes to monitor the user's pulse. The mounting portion 8201 may include sensors, such as a temperature sensor, a pressure sensor, or an acceleration sensor so that the user's biological information can be displayed on the display portion 8204. The main body 8203 may be configured to sense the movement of the user's head or the like to move an image displayed on the display portion 8204 in synchronization with the movement of the user's head or the like.

The semiconductor device of one embodiment of the present invention can be used for an integrated circuit included in the main body 8203.

At least part of this embodiment can be implemented in combination with any of the embodiments described in this specification as appropriate.

Embodiment 14

In this embodiment, application examples of an RF tag using the semiconductor device of one embodiment of the present invention are described with reference to FIGS. 48A to 48F.

<Application Examples of RF Tag>

The RF tag is widely used and can be provided for, for example, products such as bills, coins, securities, bearer bonds, documents (e.g., driver's licenses or resident's cards, see FIG. 48A), vehicles (e.g., bicycles, see FIG. 48B), packaging containers (e.g., wrapping paper or bottles, see FIG. 48C), recording media (e.g., DVD or video tapes, see FIG. 48D), personal belongings (e.g., bags or glasses, see FIG. 48E), foods, plants, animals, human bodies, clothing, household goods, medical supplies such as medicine and chemicals, products such as electronic devices (e.g., liquid crystal display devices, EL display devices, television sets, or cellular phones), or tags on products (see FIG. 48F).

An RF tag 4000 of one embodiment of the present invention is fixed to a product by being attached to a surface thereof or embedded therein. For example, the RF tag 4000 is fixed to each product by being embedded in paper of a book, or embedded in an organic resin of a package. Since the RF tag 4000 of one embodiment of the present invention can be reduced in size, thickness, and weight, it can be fixed to a product without spoiling the design of the product. Furthermore, bills, coins, securities, bearer bonds, documents, or the like can have an identification function by being provided with the RF tag 4000 of one embodiment of the present invention, and the identification function can be utilized to prevent counterfeiting. Moreover, the efficiency of a system such as an inspection system can be improved by providing the RF tag of one embodiment of the present invention for packaging containers, recording media, personal belongings, foods, clothing, household goods, electronic devices, or the like. Vehicles can also have higher security against theft or the like by being provided with the RF tag of one embodiment of the present invention.

As described above, by using the RF tag including the semiconductor device of one embodiment of the present invention for each application described in this embodiment, power for operation such as writing or reading of data can be reduced, which results in an increase in the maximum communication distance. Moreover, data can be held for an extremely long period even in the state where power is not supplied; thus, the RF tag can be preferably used for application in which data is not frequently written or read.

This embodiment can be combined as appropriate with any of the other embodiments in this specification.

This application is based on Japanese Patent Application serial no. 2015-025593 filed with Japan Patent Office on Feb. 12, 2015, the entire contents of which are hereby incorporated by reference. 

What is claimed is:
 1. A semiconductor device comprising: an oxide semiconductor; a first conductor; a second conductor; a third conductor; a first insulator; and a second insulator, wherein the first conductor comprises: a first region; a second region; and a third region, wherein the first region comprises a region where the first conductor overlaps with the oxide semiconductor with the first insulator interposed between the first conductor and the oxide semiconductor, wherein the second region comprises a region where the first conductor overlaps with the second conductor with the first insulator and the second insulator interposed between the first conductor and the second conductor, wherein the third region comprises a region where the first conductor overlaps with the third conductor with the first insulator and the second insulator interposed between the first conductor and the third conductor, wherein the oxide semiconductor comprises: a fourth region comprising a region where the oxide semiconductor is in contact with the second conductor; and a fifth region comprising a region where the oxide semiconductor is in contact with the third conductor, wherein the second conductor comprises: a sixth region; and a seventh region, wherein the third conductor comprises: an eighth region; and a ninth region, wherein the seventh region faces the eighth region with the first conductor and the first insulator interposed between the seventh region and the eighth region, and wherein the seventh region is thinner than the sixth region and the eighth region is thinner than the ninth region.
 2. The semiconductor device according to claim 1, wherein the first conductor is a stacked-layer film comprising a conductor that is less likely to transmit oxygen.
 3. The semiconductor device according to claim 1, wherein the second conductor and the third conductor are each a stacked-layer film comprising a conductor that is less likely to transmit oxygen.
 4. The semiconductor device according to claim 1, wherein the oxide semiconductor comprises a first oxide semiconductor layer and a second oxide semiconductor layer, and wherein the first oxide semiconductor layer overlaps with the second oxide semiconductor layer.
 5. The semiconductor device according to claim 1, wherein the first conductor comprises a region serving as a gate electrode of a transistor, and wherein the transistor comprises a gate line width of 5 nm or greater and 60 nm or smaller.
 6. A method for manufacturing a semiconductor device, comprising the steps of: forming a first oxide semiconductor over a first insulator; forming a second oxide semiconductor over the first oxide semiconductor; etching part of the first oxide semiconductor and part of the second oxide semiconductor to form an island-shaped oxide semiconductor layer comprising the first oxide semiconductor and the second oxide semiconductor; forming, over the first insulator and the island-shaped oxide semiconductor layer, a first conductor comprising a first region, a second region, a third region, a fourth region, and a fifth region; forming a resist over the second region, the third region, the fourth region, and the fifth region; etching the first region of the first conductor; reducing the resist to form a resist over the fourth region and the fifth region; etching the first region, the second region, and the third region of the first conductor and then etching the entire first region of the first conductor to form a first conductive layer and a second conductive layer; forming a second conductor over the first insulator, the first conductive layer, and the second conductive layer; forming a second photoresist over the second conductor; etching the second conductor to form a third conductive layer; forming a second insulator over the first insulator and the third conductive layer; forming an opening reaching a top surface of the first insulator and an opening reaching a top surface of the island-shaped oxide semiconductor layer in the second insulator and the third conductive layer to separate the third conductive layer into a fourth conductive layer and a fifth conductive layer; forming a third oxide semiconductor over the second insulator and the island-shaped oxide semiconductor layer; forming a third insulator over the third oxide semiconductor; forming a third conductor over the third insulator; etching part of the third conductor to form a sixth conductive layer; and forming a fourth insulator over the second insulator and the sixth conductive layer.
 7. The method for manufacturing a semiconductor device, according to claim 6, wherein the third conductive layer is less likely to transmit oxygen than the first conductive layer and the second conductive layer.
 8. The method for manufacturing a semiconductor device, according to claim 6, wherein the third conductive layer is formed to cover a top surface and a side surface of the first conductive layer and a top surface and a side surface the second conductive layer.
 9. The method for manufacturing a semiconductor device, according to claim 6, further comprising the steps of: forming, over the third conductor, a fourth conductor that is less likely to transmit oxygen than the third conductor; forming, below the third conductor, a fifth conductor that is less likely to transmit oxygen than the third conductor; and etching part of the third conductor, part of the fourth conductor, and part of the fifth conductor to form a seventh conductive layer.
 10. The method for manufacturing a semiconductor device, according to claim 6, further comprising the step of: forming, as the fourth insulator, an insulator that is less likely to transmit oxygen than the first insulator, the second insulator, and the third insulator.
 11. The method for manufacturing a semiconductor device, according to claim 6, wherein the second insulator has a surface planarized by chemical mechanical polishing treatment.
 12. The method for manufacturing a semiconductor device, according to claim 6, wherein the fourth region comprises a sixth region and seventh region, wherein the fifth region comprises a eighth region and ninth region, wherein the seventh region faces the eighth region with the sixth conductive layer and the third insulator interposed between the seventh region and the eighth region, and wherein the seventh region is thinner than the sixth region and the eighth region is thinner than the ninth region.
 13. A method for manufacturing a semiconductor device, comprising the steps of: forming a first oxide semiconductor over a first insulator; forming a second oxide semiconductor over the first oxide semiconductor; etching part of the first oxide semiconductor and part of the second oxide semiconductor to form an island-shaped oxide semiconductor layer comprising the first oxide semiconductor and the second oxide semiconductor; forming, over the first insulator and the island-shaped oxide semiconductor layer, a first conductor comprising a first region, a second region, a third region, a fourth region, and a fifth region; forming a resist over the second region, the third region, the fourth region, and the fifth region; etching the first region of the first conductor; reducing the resist to form a resist over the fourth region and the fifth region; etching the first region, the second region, and the third region of the first conductor and then etching the entire first region of the first conductor to form a first conductive layer and a second conductive layer; forming a second conductor over the first insulator, the first conductive layer, and the second conductive layer; forming a second photoresist over the second conductor; etching the second conductor to form a third conductive layer; forming a second insulator over the first insulator and the third conductive layer; forming an opening reaching a surface of the first insulator and an opening reaching a surface of the island-shaped oxide semiconductor layer in the second insulator and the third conductive layer to separate the third conductive layer into a fourth conductive layer and a fifth conductive layer; forming a third oxide semiconductor over the second insulator and the island-shaped oxide semiconductor layer; forming a third insulator over the third oxide semiconductor; forming a third conductor over the third insulator; etching part of the third conductor to form a sixth conductive layer; forming a fourth insulator over the second insulator and the sixth conductive layer using plasma comprising oxygen to add the oxygen in the plasma into the second insulator as excess oxygen; performing heat treatment to move the excess oxygen to the second oxide semiconductor; and forming a fifth insulator over the fourth insulator.
 14. The method for manufacturing a semiconductor device, according to claim 13, wherein the third conductive layer is less likely to transmit oxygen than the first conductive layer and the second conductive layer.
 15. The method for manufacturing a semiconductor device, according to claim 13, wherein the third conductive layer is formed to cover a top surface and a side surface of the first conductive layer and a top surface and a side surface of the second conductive layer.
 16. The method for manufacturing a semiconductor device, according to claim 13, further comprising the steps of: forming, over the third conductor, a fourth conductor that is less likely to transmit oxygen than the third conductor; forming, below the third conductor, a fifth conductor that is less likely to transmit oxygen than the third conductor; and etching part of the third conductor, part of the fourth conductor, and part of the fifth conductor to form a seventh conductive layer.
 17. The method for manufacturing a semiconductor device, according to claim 13, further comprising the step of: forming, as the fourth insulator, an insulator that is less likely to transmit oxygen than the first insulator, the second insulator, and the third insulator.
 18. The method for manufacturing a semiconductor device, according to claim 13, wherein the second insulator has a surface planarized by chemical mechanical polishing treatment.
 19. The method for manufacturing a semiconductor device, according to claim 13, wherein the fourth region comprises a sixth region and seventh region, wherein the fifth region comprises a eighth region and ninth region, wherein the seventh region faces the eighth region with the sixth conductive layer and the third insulator interposed between the seventh region and the eighth region, and wherein the seventh region is thinner than the sixth region and the eighth region is thinner than the ninth region. 